Searched hist:"584 dc4095ed2e5d70146c5cb220fac18645798d1" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | zynq-zturn-myir.dts | 584dc4095ed2e5d70146c5cb220fac18645798d1 Mon Jul 03 11:41:36 UTC 2017 Alexander Graf <agraf@suse.de> zynq: Add Z-Turn board
The Z-Turn board is a low cost development board based on the
Xilinx Zynq SoC. While it's powerful and quite versatile, it
so far lacked upstream support.
This patch adds basic support for the Z-Turn. It does however
for now miss enablement for MIO51 reset which means that USB
and ethernet don't work. For that either FSBL or SPL need to
be adjusted. The SPL part will follow later.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
| H A D | Makefile | 584dc4095ed2e5d70146c5cb220fac18645798d1 Mon Jul 03 11:41:36 UTC 2017 Alexander Graf <agraf@suse.de> zynq: Add Z-Turn board
The Z-Turn board is a low cost development board based on the
Xilinx Zynq SoC. While it's powerful and quite versatile, it
so far lacked upstream support.
This patch adds basic support for the Z-Turn. It does however
for now miss enablement for MIO51 reset which means that USB
and ethernet don't work. For that either FSBL or SPL need to
be adjusted. The SPL part will follow later.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
| /rk3399_rockchip-uboot/configs/ |
| H A D | zynq_z_turn_defconfig | 584dc4095ed2e5d70146c5cb220fac18645798d1 Mon Jul 03 11:41:36 UTC 2017 Alexander Graf <agraf@suse.de> zynq: Add Z-Turn board
The Z-Turn board is a low cost development board based on the
Xilinx Zynq SoC. While it's powerful and quite versatile, it
so far lacked upstream support.
This patch adds basic support for the Z-Turn. It does however
for now miss enablement for MIO51 reset which means that USB
and ethernet don't work. For that either FSBL or SPL need to
be adjusted. The SPL part will follow later.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|