Searched hist:"5668 db72b724dc256d9b300f6938a08625624a48" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/ti/k3/board/j784s4/ |
| H A D | board.mk | 5668db72b724dc256d9b300f6938a08625624a48 Thu Jan 12 15:32:33 UTC 2023 Andrew Davis <afd@ti.com> feat(ti): set snoop-delayed exclusive handling on A72 cores
Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by the
core's SCU delaying to check for the corresponding atomic monitor state.
TI SoCs take the second approach. Set the snoop-delayed exclusive handling
bit to inform the core it needs to delay responses to perform this check.
As J784s4 is currently the only SoC with multiple A72 clusters, limit
this delay to only that device.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I875f64e4f53d47a9a0ccbf3415edc565be7f84d9
|
| /rk3399_ARM-atf/include/lib/cpus/aarch32/ |
| H A D | cortex_a72.h | 5668db72b724dc256d9b300f6938a08625624a48 Thu Jan 12 15:32:33 UTC 2023 Andrew Davis <afd@ti.com> feat(ti): set snoop-delayed exclusive handling on A72 cores
Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by the
core's SCU delaying to check for the corresponding atomic monitor state.
TI SoCs take the second approach. Set the snoop-delayed exclusive handling
bit to inform the core it needs to delay responses to perform this check.
As J784s4 is currently the only SoC with multiple A72 clusters, limit
this delay to only that device.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I875f64e4f53d47a9a0ccbf3415edc565be7f84d9
|
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a72.h | 5668db72b724dc256d9b300f6938a08625624a48 Thu Jan 12 15:32:33 UTC 2023 Andrew Davis <afd@ti.com> feat(ti): set snoop-delayed exclusive handling on A72 cores
Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by the
core's SCU delaying to check for the corresponding atomic monitor state.
TI SoCs take the second approach. Set the snoop-delayed exclusive handling
bit to inform the core it needs to delay responses to perform this check.
As J784s4 is currently the only SoC with multiple A72 clusters, limit
this delay to only that device.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I875f64e4f53d47a9a0ccbf3415edc565be7f84d9
|