Searched hist:"508 d71108a06c7fce2eeef78659b9b7739cee6eb" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a76.S | 508d71108a06c7fce2eeef78659b9b7739cee6eb Thu Feb 21 17:35:07 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> Add workaround for errata 1130799 for Cortex-A76
TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to
prevent this.
Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 508d71108a06c7fce2eeef78659b9b7739cee6eb Thu Feb 21 17:35:07 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> Add workaround for errata 1130799 for Cortex-A76
TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to
prevent this.
Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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