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/rk3399_rockchip-uboot/include/configs/
H A DMPC8349ITX.h507e2d79c91441a0bb2cd3d0c31c8bfe3f8cec07 Mon Mar 24 17:00:59 UTC 2008 Joe D'Abbraccio <ljd015@freescale.com> Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock

With the original value of 1/2 clock cycle delay, the system ran relatively
stable except when we run benchmarks that are intensive users of memory.
When I run samba connected disk with a HDBENCH test, the system locks-up
or reboots sporadically.

Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>