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/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.c4d5d98c77c0c3276cf6b9f39e6efbf5eccf44d6c Wed Sep 28 01:19:30 UTC 2016 Caesar Wang <wxt@rock-chips.com> rockchip: fixes the clock select and divide register for rk3399

As the new RK3399TRM v1.1, there are some wrong set for CRU_CLKSEL_CON
register.

As the CRU_CLKSEL_CON96～107 high 16-bit isn't write mask and the
CRU_CLKSEL_CON offset is 0x100,not 0x80.

Change-Id: Ie127e9de74b87100af9a0150aad43e89e4972529
H A Dsoc.h4d5d98c77c0c3276cf6b9f39e6efbf5eccf44d6c Wed Sep 28 01:19:30 UTC 2016 Caesar Wang <wxt@rock-chips.com> rockchip: fixes the clock select and divide register for rk3399

As the new RK3399TRM v1.1, there are some wrong set for CRU_CLKSEL_CON
register.

As the CRU_CLKSEL_CON96～107 high 16-bit isn't write mask and the
CRU_CLKSEL_CON offset is 0x100,not 0x80.

Change-Id: Ie127e9de74b87100af9a0150aad43e89e4972529