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| /rk3399_rockchip-uboot/drivers/mtd/spi/ |
| H A D | spi-nor-core.c | 4c6d72aa664089516d474396dce7853e75c84d2b Wed Jul 31 07:04:15 UTC 2024 Jon Lin <jon.lin@rock-chips.com> mtd: spi-nor-ids: Support BFPT_DWORD15_QER_SR2_BIT1_WR
QE is bit 1 of the status register 2. Status register 1 is read using
Read Status instruction 05h. Status register 2 is read using instruction
35h, and status register 3 is read using instruction 15h. QE is set via
write Status Register instruction 31h with one data byte where bit 1 is
one. It is cleared via Write Status Register instruction 31h with one
data byte where bit 1 is zero.
Change-Id: I4bfab50210dc8dbc7818c41d15b516be49640706
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
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