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| /rk3399_rockchip-uboot/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 4497861ae7e52dda4dd13db860df4cc0fa7dd852 Fri Dec 02 01:38:12 UTC 2011 Shaohui Xie <Shaohui.Xie@freescale.com> p2041rdb: fix serdes clock map
Description of SerDes clock Bank2 setting in p2041 hardware specification
is wrong, the clock map which based on it is wrong either, so fix the
serdes clock map.
wrong setting of SERDES Reference Clocks Bank2:
SW2[5:6] = ON OFF =>100MHz for PCI mode
SW2[5:6] = OFF ON =>125MHz for SGMII mode
right setting of SERDES Reference Clocks Bank2:
SW2[5:6] = OFF OFF =>100MHz for PCI mode
SW2[5:6] = OFF ON =>125MHz for SGMII mode
SW2[5:6] = ON OFF =>156.25MHZ
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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