Searched hist:"42920 aa743901395431f8c0ad0b79d0d79ef4ade" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_x3.S | 42920aa743901395431f8c0ad0b79d0d79ef4ade Thu Jul 10 14:59:00 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> fix(cpus): workaround for Cortex-X3 erratum 3213672
Cortex-X3 erratum 3213672 is a Cat B erratum that applies to
r0p0, r1p0, r1p1 and r1p2. It is still open.
This erratum can be worked around by setting CPUACTLR_EL1[36]
before enabling icache.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia1c03217f4e1816b4e8754a090cf5bc17546be40
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 42920aa743901395431f8c0ad0b79d0d79ef4ade Thu Jul 10 14:59:00 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> fix(cpus): workaround for Cortex-X3 erratum 3213672
Cortex-X3 erratum 3213672 is a Cat B erratum that applies to
r0p0, r1p0, r1p1 and r1p2. It is still open.
This erratum can be worked around by setting CPUACTLR_EL1[36]
before enabling icache.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia1c03217f4e1816b4e8754a090cf5bc17546be40
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 42920aa743901395431f8c0ad0b79d0d79ef4ade Thu Jul 10 14:59:00 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> fix(cpus): workaround for Cortex-X3 erratum 3213672
Cortex-X3 erratum 3213672 is a Cat B erratum that applies to
r0p0, r1p0, r1p1 and r1p2. It is still open.
This erratum can be worked around by setting CPUACTLR_EL1[36]
before enabling icache.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia1c03217f4e1816b4e8754a090cf5bc17546be40
|