Searched hist:"3 de5947c1b98db216b1790c9d20815302373a4c5" (Results 1 – 2 of 2) sorted by relevance
| /optee_os/lib/libutils/ext/arch/riscv/ |
| H A D | atomic_rv.S | 3de5947c1b98db216b1790c9d20815302373a4c5 Mon Jan 09 10:19:05 UTC 2023 Marouene Boubakri <marouene.boubakri@nxp.com> libutils: riscv: provide atomic_rv.S
Implement atomic_inc32() and atomic_dec32() in atomic_rv.S.
The implementation is based on atomic addition instruction
with acquire and release suffix to add additional memory
order constraints.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| H A D | sub.mk | 3de5947c1b98db216b1790c9d20815302373a4c5 Mon Jan 09 10:19:05 UTC 2023 Marouene Boubakri <marouene.boubakri@nxp.com> libutils: riscv: provide atomic_rv.S
Implement atomic_inc32() and atomic_dec32() in atomic_rv.S.
The implementation is based on atomic addition instruction
with acquire and release suffix to add additional memory
order constraints.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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