| #
ae9b3ff9 |
| 20-Jun-2023 |
Alvin Chang <alvinga@andestech.com> |
libutils: riscv: Implement _mount() and __ftrace_return()
When the core and TA are compiled with the -pg option, the compiler inserts a call to _mcount() into every function prologue. It can be used
libutils: riscv: Implement _mount() and __ftrace_return()
When the core and TA are compiled with the -pg option, the compiler inserts a call to _mcount() into every function prologue. It can be used to trace the function calls such as ftrace.
Implement the _mount() to prepare the necessary parameters for ftrace. The __ftrace_return() is also implemented for returning from ftrace.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
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| #
3de5947c |
| 09-Jan-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
libutils: riscv: provide atomic_rv.S
Implement atomic_inc32() and atomic_dec32() in atomic_rv.S. The implementation is based on atomic addition instruction with acquire and release suffix to add add
libutils: riscv: provide atomic_rv.S
Implement atomic_inc32() and atomic_dec32() in atomic_rv.S. The implementation is based on atomic addition instruction with acquire and release suffix to add additional memory order constraints.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
ad0ae800 |
| 27-Dec-2021 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
riscv: create makefiles and directories tree for riscv
This commits creates the very first makefiles, directories and subdirectories for RISC-V port. It also creates a new platform flavor named plat
riscv: create makefiles and directories tree for riscv
This commits creates the very first makefiles, directories and subdirectories for RISC-V port. It also creates a new platform flavor named plat-spike. Spike is a reference functional RISC-V ISA simulator which provides full system emulation and it is developed alongside the RISC-V toolchain.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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