Searched hist:"3 db1b3e3179fb98fba226bae3b7d6d1f5723e8ac" (Results 1 – 4 of 4) sorted by relevance
| /optee_os/core/arch/riscv/kernel/ |
| H A D | arch_scall.c | 3db1b3e3179fb98fba226bae3b7d6d1f5723e8ac Tue Jul 18 07:07:59 UTC 2023 Alvin Chang <alvinga@andestech.com> core: riscv: Support Privileged Access Never by CSR status.SUM bit
The SUM (Supervisor User Memory access) bit modifies the privilege with
which S-mode loads and stores the user virtual memory. When SUM bit is
0, S-mode accesses to pages whose U bit of corresponding PTE is set will
fault. When SUM bit is 1, these accesses are permitted.
When CFG_PAN is disabled in RISC-V architecture, the status.SUM bit is
initialized as 1 by default. Therefore all accesses to user pages will
succeed. When CFG_PAN is enabled, the status.SUM bit is initialized as
0, and only set to 1 when kernel needs to access user pages.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
|
| H A D | thread_arch.c | 3db1b3e3179fb98fba226bae3b7d6d1f5723e8ac Tue Jul 18 07:07:59 UTC 2023 Alvin Chang <alvinga@andestech.com> core: riscv: Support Privileged Access Never by CSR status.SUM bit
The SUM (Supervisor User Memory access) bit modifies the privilege with
which S-mode loads and stores the user virtual memory. When SUM bit is
0, S-mode accesses to pages whose U bit of corresponding PTE is set will
fault. When SUM bit is 1, these accesses are permitted.
When CFG_PAN is disabled in RISC-V architecture, the status.SUM bit is
initialized as 1 by default. Therefore all accesses to user pages will
succeed. When CFG_PAN is enabled, the status.SUM bit is initialized as
0, and only set to 1 when kernel needs to access user pages.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
|
| /optee_os/core/arch/riscv/include/kernel/ |
| H A D | user_access_arch.h | 3db1b3e3179fb98fba226bae3b7d6d1f5723e8ac Tue Jul 18 07:07:59 UTC 2023 Alvin Chang <alvinga@andestech.com> core: riscv: Support Privileged Access Never by CSR status.SUM bit
The SUM (Supervisor User Memory access) bit modifies the privilege with
which S-mode loads and stores the user virtual memory. When SUM bit is
0, S-mode accesses to pages whose U bit of corresponding PTE is set will
fault. When SUM bit is 1, these accesses are permitted.
When CFG_PAN is disabled in RISC-V architecture, the status.SUM bit is
initialized as 1 by default. Therefore all accesses to user pages will
succeed. When CFG_PAN is enabled, the status.SUM bit is initialized as
0, and only set to 1 when kernel needs to access user pages.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
|
| /optee_os/mk/ |
| H A D | config.mk | 3db1b3e3179fb98fba226bae3b7d6d1f5723e8ac Tue Jul 18 07:07:59 UTC 2023 Alvin Chang <alvinga@andestech.com> core: riscv: Support Privileged Access Never by CSR status.SUM bit
The SUM (Supervisor User Memory access) bit modifies the privilege with
which S-mode loads and stores the user virtual memory. When SUM bit is
0, S-mode accesses to pages whose U bit of corresponding PTE is set will
fault. When SUM bit is 1, these accesses are permitted.
When CFG_PAN is disabled in RISC-V architecture, the status.SUM bit is
initialized as 1 by default. Therefore all accesses to user pages will
succeed. When CFG_PAN is enabled, the status.SUM bit is initialized as
0, and only set to 1 when kernel needs to access user pages.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
|