Searched hist:"35 e561d87c7e50ccdbb8048ffa10a7f2b14756fb" (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/arch/arm/plat-imx/registers/ |
| H A D | imx93.h | 35e561d87c7e50ccdbb8048ffa10a7f2b14756fb Fri Aug 11 11:27:13 UTC 2023 Sahil Malhotra <sahil.malhotra@nxp.com> drivers: ele: enable TRUST MU in OP-TEE for i.MX93-EVK/i.MX91-EVK
There is TRUST MU available on i.MX91 and i.MX93 platforms.
TRUST MU can be used to access some HW features of Edgelock Enclave which
Normal MU cannot, but for now it is configured to be used to communicate
with ELE FW.
So Kernel will use Normal MU and OP-TEE will use TRUST MU.
There is special setup needed to write to Trust MU.
* First for TRUST-MU we must write a valid command to TR0 before we can
write any of the remaining registers, and TR15 is reserved for special
USM command.
* The CMD field for TR0 is bits 31:26 and must be greater than
the value of the watermark set in SCM_CR2[31:22]. Typically
if you just set the MSB (bit 31) its enough.
* SIZE must be programmed in bits 19:16 of TR0, we cannot write
TRn past the specified size in this bit field
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
|
| /optee_os/core/drivers/imx/mu/ |
| H A D | imx_mu.c | 35e561d87c7e50ccdbb8048ffa10a7f2b14756fb Fri Aug 11 11:27:13 UTC 2023 Sahil Malhotra <sahil.malhotra@nxp.com> drivers: ele: enable TRUST MU in OP-TEE for i.MX93-EVK/i.MX91-EVK
There is TRUST MU available on i.MX91 and i.MX93 platforms.
TRUST MU can be used to access some HW features of Edgelock Enclave which
Normal MU cannot, but for now it is configured to be used to communicate
with ELE FW.
So Kernel will use Normal MU and OP-TEE will use TRUST MU.
There is special setup needed to write to Trust MU.
* First for TRUST-MU we must write a valid command to TR0 before we can
write any of the remaining registers, and TR15 is reserved for special
USM command.
* The CMD field for TR0 is bits 31:26 and must be greater than
the value of the watermark set in SCM_CR2[31:22]. Typically
if you just set the MSB (bit 31) its enough.
* SIZE must be programmed in bits 19:16 of TR0, we cannot write
TRn past the specified size in this bit field
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
|