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/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_memctrl.c34a6610aeb8e1e976c3afc65155210e919633927 Wed Mar 07 08:36:30 UTC 2018 Puneet Saxena <puneets@nvidia.com> Tegra194: memctrl: set reorder depth limit for PCIE blocks

HW bug in third party PCIE IP - PCIE datapath hangs when there are
more than 28 outstanding requests on data backbone for x1 controller.

Suggested SW WAR is to limit reorder_depth_limit to 16 for
PCIE 1W/2AW/3W clients.

Change-Id: Id5448251c35d2a93f66a8b5835ae4044f5cef067
Signed-off-by: Puneet Saxena <puneets@nvidia.com>