1719fdb6eSVarun Wadekar /* 2c766adceSPritesh Raithatha * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3719fdb6eSVarun Wadekar * 4719fdb6eSVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 5719fdb6eSVarun Wadekar */ 6719fdb6eSVarun Wadekar 7f32e8525SVarun Wadekar #include <assert.h> 8f32e8525SVarun Wadekar #include <common/bl_common.h> 9f32e8525SVarun Wadekar #include <mce.h> 10719fdb6eSVarun Wadekar #include <memctrl_v2.h> 11f32e8525SVarun Wadekar #include <tegra_platform.h> 12*08e60f80SVarun Wadekar #include <tegra_private.h> 13719fdb6eSVarun Wadekar 14719fdb6eSVarun Wadekar /******************************************************************************* 15a391d494SPritesh Raithatha * Array to hold MC context for Tegra194 16a391d494SPritesh Raithatha ******************************************************************************/ 17a391d494SPritesh Raithatha static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = { 18a391d494SPritesh Raithatha _START_OF_TABLE_, 19a391d494SPritesh Raithatha mc_smmu_bypass_cfg, /* TBU settings */ 20a391d494SPritesh Raithatha _END_OF_TABLE_, 21a391d494SPritesh Raithatha }; 22a391d494SPritesh Raithatha 23a391d494SPritesh Raithatha /******************************************************************************* 24a391d494SPritesh Raithatha * Handler to return the pointer to the MC's context struct 25a391d494SPritesh Raithatha ******************************************************************************/ plat_memctrl_get_sys_suspend_ctx(void)26*08e60f80SVarun Wadekarmc_regs_t *plat_memctrl_get_sys_suspend_ctx(void) 27a391d494SPritesh Raithatha { 28a391d494SPritesh Raithatha /* index of _END_OF_TABLE_ */ 29a391d494SPritesh Raithatha tegra194_mc_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_mc_context) - 1U; 30a391d494SPritesh Raithatha 31a391d494SPritesh Raithatha return tegra194_mc_context; 32a391d494SPritesh Raithatha } 33a391d494SPritesh Raithatha 34a391d494SPritesh Raithatha /******************************************************************************* 35*08e60f80SVarun Wadekar * Handler to restore platform specific settings to the memory controller 36719fdb6eSVarun Wadekar ******************************************************************************/ plat_memctrl_restore(void)37*08e60f80SVarun Wadekarvoid plat_memctrl_restore(void) 38*08e60f80SVarun Wadekar { 39*08e60f80SVarun Wadekar UNUSED_FUNC_NOP(); /* do nothing */ 40*08e60f80SVarun Wadekar } 41719fdb6eSVarun Wadekar 42719fdb6eSVarun Wadekar /******************************************************************************* 43*08e60f80SVarun Wadekar * Handler to program platform specific settings to the memory controller 44719fdb6eSVarun Wadekar ******************************************************************************/ plat_memctrl_setup(void)45*08e60f80SVarun Wadekarvoid plat_memctrl_setup(void) 46719fdb6eSVarun Wadekar { 47*08e60f80SVarun Wadekar UNUSED_FUNC_NOP(); /* do nothing */ 48719fdb6eSVarun Wadekar } 494e697b77SSteven Kao 504e697b77SSteven Kao /******************************************************************************* 514e697b77SSteven Kao * Handler to program the scratch registers with TZDRAM settings for the 524e697b77SSteven Kao * resume firmware 534e697b77SSteven Kao ******************************************************************************/ plat_memctrl_tzdram_setup(uint64_t phys_base,uint64_t size_in_bytes)544e697b77SSteven Kaovoid plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) 554e697b77SSteven Kao { 5695397d96SSteven Kao uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0); 577e491133SVarun Wadekar uint32_t phys_base_lo = (uint32_t)phys_base & 0xFFF00000; 587e491133SVarun Wadekar uint32_t phys_base_hi = (uint32_t)(phys_base >> 32); 5995397d96SSteven Kao 604e697b77SSteven Kao /* 6195397d96SSteven Kao * Check TZDRAM carveout register access status. Setup TZDRAM fence 6295397d96SSteven Kao * only if access is enabled. 634e697b77SSteven Kao */ 6495397d96SSteven Kao if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) == 6595397d96SSteven Kao SECURITY_CFG_WRITE_ACCESS_ENABLE) { 664e697b77SSteven Kao 674e697b77SSteven Kao /* 684e697b77SSteven Kao * Setup the Memory controller to allow only secure accesses to 694e697b77SSteven Kao * the TZDRAM carveout 704e697b77SSteven Kao */ 714e697b77SSteven Kao INFO("Configuring TrustZone DRAM Memory Carveout\n"); 724e697b77SSteven Kao 737e491133SVarun Wadekar tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base_lo); 747e491133SVarun Wadekar tegra_mc_write_32(MC_SECURITY_CFG3_0, phys_base_hi); 754e697b77SSteven Kao tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); 764e697b77SSteven Kao 774e697b77SSteven Kao /* 784e697b77SSteven Kao * MCE propagates the security configuration values across the 794e697b77SSteven Kao * CCPLEX. 804e697b77SSteven Kao */ 814e697b77SSteven Kao (void)mce_update_gsc_tzdram(); 824e697b77SSteven Kao } 834e697b77SSteven Kao } 84