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| /rk3399_ARM-atf/drivers/cadence/emmc/ |
| H A D | cdns_sdmmc.c | 2fcb37db8384bfb7a08edcd024f5ca4e245dc2df Tue Jul 29 09:29:43 UTC 2025 Boon Khai Ng <boon.khai.ng@altera.com> fix(intel): add memory alignment at cadence SD/eMMC driver's descriptor
When compile using arm gcc compiler with versions 12 above,
the cadence SD/eMMC driver will failed with ADMA error. When
sending MMC command. The memory is not aligned correctly
when using different version of gcc.
The descriptor memory must be aligned to 4 byte boundary
with 2 least significant bits set to 0 in 32-bit ADMA
addressing mode and aligned to 8 byte boundary with
3 least significant bits set to 0 in 64-bit ADMA
addresing mode.
Since 8 byte boundary is common to both 4 byte and
8 byte boundary hence aligning the descriptor
memory with 8 byte boundary.
Change-Id: Ie56d2aef22b4e4ef0fa516b9cda53b33d6316cb7
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
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