Searched hist:"1 f866fc9763370503a6596cafada9e5a4d6531f5" (Results 1 – 8 of 8) sorted by relevance
| /rk3399_ARM-atf/include/drivers/arm/ |
| H A D | dsu.h | 1f866fc9763370503a6596cafada9e5a4d6531f5 Thu Sep 18 09:31:10 UTC 2025 Amr Mohamed <amr.mohamed@arm.com> feat(dsu): enable PMU registers access at EL1
- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
counting in the secure state.
Change-Id: If3eb6e997330ae86f45760e0e862c003861f3d66
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
|
| /rk3399_ARM-atf/drivers/arm/dsu/ |
| H A D | dsu.c | 1f866fc9763370503a6596cafada9e5a4d6531f5 Thu Sep 18 09:31:10 UTC 2025 Amr Mohamed <amr.mohamed@arm.com> feat(dsu): enable PMU registers access at EL1
- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
counting in the secure state.
Change-Id: If3eb6e997330ae86f45760e0e862c003861f3d66
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
|
| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | arch_helpers.h | 1f866fc9763370503a6596cafada9e5a4d6531f5 Thu Sep 18 09:31:10 UTC 2025 Amr Mohamed <amr.mohamed@arm.com> feat(dsu): enable PMU registers access at EL1
- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
counting in the secure state.
Change-Id: If3eb6e997330ae86f45760e0e862c003861f3d66
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
|
| H A D | arch.h | 1f866fc9763370503a6596cafada9e5a4d6531f5 Thu Sep 18 09:31:10 UTC 2025 Amr Mohamed <amr.mohamed@arm.com> feat(dsu): enable PMU registers access at EL1
- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
counting in the secure state.
Change-Id: If3eb6e997330ae86f45760e0e862c003861f3d66
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | firmware-design.rst | 1f866fc9763370503a6596cafada9e5a4d6531f5 Thu Sep 18 09:31:10 UTC 2025 Amr Mohamed <amr.mohamed@arm.com> feat(dsu): enable PMU registers access at EL1
- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
counting in the secure state.
Change-Id: If3eb6e997330ae86f45760e0e862c003861f3d66
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
|
| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | arch_helpers.h | 1f866fc9763370503a6596cafada9e5a4d6531f5 Thu Sep 18 09:31:10 UTC 2025 Amr Mohamed <amr.mohamed@arm.com> feat(dsu): enable PMU registers access at EL1
- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
counting in the secure state.
Change-Id: If3eb6e997330ae86f45760e0e862c003861f3d66
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
|
| H A D | arch.h | 1f866fc9763370503a6596cafada9e5a4d6531f5 Thu Sep 18 09:31:10 UTC 2025 Amr Mohamed <amr.mohamed@arm.com> feat(dsu): enable PMU registers access at EL1
- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
counting in the secure state.
Change-Id: If3eb6e997330ae86f45760e0e862c003861f3d66
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
|
| /rk3399_ARM-atf/docs/getting_started/ |
| H A D | build-options.rst | 1f866fc9763370503a6596cafada9e5a4d6531f5 Thu Sep 18 09:31:10 UTC 2025 Amr Mohamed <amr.mohamed@arm.com> feat(dsu): enable PMU registers access at EL1
- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
counting in the secure state.
Change-Id: If3eb6e997330ae86f45760e0e862c003861f3d66
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
|