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/rk3399_rockchip-uboot/board/freescale/mpc8569mds/
H A Dddr.c1b5291dddf5f16c7ae10e3cb165882fa96038b26 Fri Mar 27 06:32:43 UTC 2009 Dave Liu <daveliu@freescale.com> 85xx: Fix the clock adjust of mpc8569mds board

Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.

Signed-off-by: Dave Liu <daveliu@freescale.com>