1765547dcSHaiying Wang /* 2765547dcSHaiying Wang * Copyright 2009 Freescale Semiconductor, Inc. 3765547dcSHaiying Wang * 4*5b8031ccSTom Rini * SPDX-License-Identifier: GPL-2.0 5765547dcSHaiying Wang */ 6765547dcSHaiying Wang 7765547dcSHaiying Wang #include <common.h> 8765547dcSHaiying Wang 95614e71bSYork Sun #include <fsl_ddr_sdram.h> 105614e71bSYork Sun #include <fsl_ddr_dimm_params.h> 11765547dcSHaiying Wang fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)12765547dcSHaiying Wangvoid fsl_ddr_board_options(memctl_options_t *popts, 13765547dcSHaiying Wang dimm_params_t *pdimm, 14765547dcSHaiying Wang unsigned int ctrl_num) 15765547dcSHaiying Wang { 16765547dcSHaiying Wang /* 17765547dcSHaiying Wang * Factors to consider for clock adjust: 18765547dcSHaiying Wang * - number of chips on bus 19765547dcSHaiying Wang * - position of slot 20765547dcSHaiying Wang * - DDR1 vs. DDR2? 21765547dcSHaiying Wang * - ??? 22765547dcSHaiying Wang * 23765547dcSHaiying Wang * This needs to be determined on a board-by-board basis. 24765547dcSHaiying Wang * 0110 3/4 cycle late 25765547dcSHaiying Wang * 0111 7/8 cycle late 26765547dcSHaiying Wang */ 271b5291ddSDave Liu popts->clk_adjust = 4; 28765547dcSHaiying Wang 29765547dcSHaiying Wang /* 30765547dcSHaiying Wang * Factors to consider for CPO: 31765547dcSHaiying Wang * - frequency 32765547dcSHaiying Wang * - ddr1 vs. ddr2 33765547dcSHaiying Wang */ 34765547dcSHaiying Wang popts->cpo_override = 0xff; 35765547dcSHaiying Wang 36765547dcSHaiying Wang /* 37765547dcSHaiying Wang * Factors to consider for write data delay: 38765547dcSHaiying Wang * - number of DIMMs 39765547dcSHaiying Wang * 40765547dcSHaiying Wang * 1 = 1/4 clock delay 41765547dcSHaiying Wang * 2 = 1/2 clock delay 42765547dcSHaiying Wang * 3 = 3/4 clock delay 43765547dcSHaiying Wang * 4 = 1 clock delay 44765547dcSHaiying Wang * 5 = 5/4 clock delay 45765547dcSHaiying Wang * 6 = 3/2 clock delay 46765547dcSHaiying Wang */ 47765547dcSHaiying Wang popts->write_data_delay = 2; 48765547dcSHaiying Wang 49765547dcSHaiying Wang /* 50b6bde930SHaiying Wang * Enable half drive strength 51765547dcSHaiying Wang */ 52b6bde930SHaiying Wang popts->half_strength_driver_enable = 1; 53b6bde930SHaiying Wang 54b6bde930SHaiying Wang /* Write leveling override */ 55b6bde930SHaiying Wang popts->wrlvl_en = 1; 56b6bde930SHaiying Wang popts->wrlvl_override = 1; 57b6bde930SHaiying Wang popts->wrlvl_sample = 0xa; 58b6bde930SHaiying Wang popts->wrlvl_start = 0x4; 59b6bde930SHaiying Wang 60b6bde930SHaiying Wang /* Rtt and Rtt_W override */ 61b6bde930SHaiying Wang popts->rtt_override = 1; 62b6bde930SHaiying Wang popts->rtt_override_value = DDR3_RTT_60_OHM; 63b6bde930SHaiying Wang popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ 64765547dcSHaiying Wang } 65