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| H A D | spl.c | 1481bafe9d3d3264f9cbb3e026475e2efe9ecb32 Mon Feb 17 09:37:51 UTC 2020 Joseph Chen <chenjh@rock-chips.com> common: spl: enable D-cache by default to improve performance
Set CONFIG_SPL_SYS_MALLOC_F_LEN enough to promise the tlb buffer
can be malloc, actually this is a way to compatible all the current
boards without adding a new configure option.
I-cache has been setup at early assembly code by default.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I7e973299eddc358cd4c15846c5de154050bf9547
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