Searched hist:"13 dcbc6f2265ac4f3ea018cdb785fb1e8d473119" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/ |
| H A D | plat_smmu.c | 13dcbc6f2265ac4f3ea018cdb785fb1e8d473119 Tue Jul 25 04:44:32 UTC 2017 Steven Kao <skao@nvidia.com> Tegra194: smmu: ISO support
The FPGA configuration is encoded in the high byte of
MISCREG_EMU_REVID. Configs GPU and MAX (encoded as
2 and 3) support the ISO SMMU, while BASE (encoded as 1)
does not. This patch implements this encoding and returns
the proper number of SMMU instances.
Change-Id: I024286b6091120c7602f63065d20ce48bcfd13fe
Signed-off-by: Steven Kao <skao@nvidia.com>
|
| H A D | platform_t194.mk | 13dcbc6f2265ac4f3ea018cdb785fb1e8d473119 Tue Jul 25 04:44:32 UTC 2017 Steven Kao <skao@nvidia.com> Tegra194: smmu: ISO support
The FPGA configuration is encoded in the high byte of
MISCREG_EMU_REVID. Configs GPU and MAX (encoded as
2 and 3) support the ISO SMMU, while BASE (encoded as 1)
does not. This patch implements this encoding and returns
the proper number of SMMU instances.
Change-Id: I024286b6091120c7602f63065d20ce48bcfd13fe
Signed-off-by: Steven Kao <skao@nvidia.com>
|
| /rk3399_ARM-atf/plat/nvidia/tegra/include/t194/ |
| H A D | tegra_def.h | 13dcbc6f2265ac4f3ea018cdb785fb1e8d473119 Tue Jul 25 04:44:32 UTC 2017 Steven Kao <skao@nvidia.com> Tegra194: smmu: ISO support
The FPGA configuration is encoded in the high byte of
MISCREG_EMU_REVID. Configs GPU and MAX (encoded as
2 and 3) support the ISO SMMU, while BASE (encoded as 1)
does not. This patch implements this encoding and returns
the proper number of SMMU instances.
Change-Id: I024286b6091120c7602f63065d20ce48bcfd13fe
Signed-off-by: Steven Kao <skao@nvidia.com>
|