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| /optee_os/core/arch/arm/plat-rockchip/ |
| H A D | main.c | 12a5f0375bcf4f5408b4c93620fe889b42577dce Wed Nov 06 23:01:05 UTC 2024 Ahmad Fatoum <ahmad@a3f.at> plat-rockchip: allow specifying DRAM via CFG options
It's currently not possible to use CFG_CORE_DYN_SHM with the Rockchip
platforms, because OP-TEE doesn't know what non-secure memory is
available; Device tree is not used and no DDR ranges are registered.
This precludes interacting with OP-TEE from barebox and U-Boot, which
currently only implement OP-TEE communication with dynamic shared
memory.
Make it possible to use CFG_CORE_DYN_SHM=y by adding two sets of config
variables to register memory:
CFG_DRAM_BASE, CFG_DRAM_SIZE:
For the main memory in the first 4G up to the MMIO range beyond
the end of the first RAM bank
CFG_NSEC_DDR_1_BASE, CFG_NSEC_DDR_1_SIZE:
For the remainder of the main memory above the MMIO regions.
OP-TEE will take care to carve out the secure memory ranges.
This has been tested on an RK3399 with barebox using OP-TEE's HWRNG TA.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
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