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/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3288.c0fd8dec7ce1771e13ce13ab4ff24023e33fea036 Wed Dec 12 10:04:52 UTC 2018 Nickey Yang <nickey.yang@rock-chips.com> clk: rockchip: rk3288: adjust gpll init_cfg

This patch adjust gpll init nr/no/nf/bw values.
keep them the same as kernel RK3066_PLL_RATE_NB(594000000, 2, 198, 4, 1)
for better clock jitter when hdmi SI test.

Change-Id: I781205d860945214f3f0957882223b8846c00773
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>