Searched hist:"0 f1411bc8dade4472ca802f46f75714e67301bb0" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/drivers/spi/ |
| H A D | mxc_spi.c | 0f1411bc8dade4472ca802f46f75714e67301bb0 Tue Apr 09 13:06:25 UTC 2013 Fabio Estevam <fabio.estevam@freescale.com> spi: mxc_spi: Set master mode for all channels
The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas re-introduced by
commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling).
Actually the glitch is happening due to always toggling between slave mode
and master mode by configuring the CHANNEL_MODE bits in this reset function.
Since the spi driver only supports master mode, set the mode for all channels
always to master mode in order to have a stable, "glitch-free" SPI clock line.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx5/ |
| H A D | imx-regs.h | 0f1411bc8dade4472ca802f46f75714e67301bb0 Tue Apr 09 13:06:25 UTC 2013 Fabio Estevam <fabio.estevam@freescale.com> spi: mxc_spi: Set master mode for all channels
The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas re-introduced by
commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling).
Actually the glitch is happening due to always toggling between slave mode
and master mode by configuring the CHANNEL_MODE bits in this reset function.
Since the spi driver only supports master mode, set the mode for all channels
always to master mode in order to have a stable, "glitch-free" SPI clock line.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx6/ |
| H A D | imx-regs.h | 0f1411bc8dade4472ca802f46f75714e67301bb0 Tue Apr 09 13:06:25 UTC 2013 Fabio Estevam <fabio.estevam@freescale.com> spi: mxc_spi: Set master mode for all channels
The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas re-introduced by
commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling).
Actually the glitch is happening due to always toggling between slave mode
and master mode by configuring the CHANNEL_MODE bits in this reset function.
Since the spi driver only supports master mode, set the mode for all channels
always to master mode in order to have a stable, "glitch-free" SPI clock line.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
|