Searched hist:"0 e985d708e8f429c1fa1f557d3eea90e32de5228" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | dsu_def.h | 0e985d708e8f429c1fa1f557d3eea90e32de5228 Tue Apr 09 15:29:01 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> DSU: Implement workaround for errata 798953
Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables high-level clock gating of the DSU to prevent this.
Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a55.S | 0e985d708e8f429c1fa1f557d3eea90e32de5228 Tue Apr 09 15:29:01 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> DSU: Implement workaround for errata 798953
Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables high-level clock gating of the DSU to prevent this.
Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| H A D | cortex_a75.S | 0e985d708e8f429c1fa1f557d3eea90e32de5228 Tue Apr 09 15:29:01 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> DSU: Implement workaround for errata 798953
Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables high-level clock gating of the DSU to prevent this.
Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| H A D | cortex_a76.S | 0e985d708e8f429c1fa1f557d3eea90e32de5228 Tue Apr 09 15:29:01 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> DSU: Implement workaround for errata 798953
Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables high-level clock gating of the DSU to prevent this.
Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 0e985d708e8f429c1fa1f557d3eea90e32de5228 Tue Apr 09 15:29:01 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> DSU: Implement workaround for errata 798953
Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables high-level clock gating of the DSU to prevent this.
Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|