Searched hist:"0 d79f4f490352f6e1500cdd12a3b0e8b17265bde" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_rockchip-uboot/include/configs/ |
| H A D | tegra114-common.h | 0d79f4f490352f6e1500cdd12a3b0e8b17265bde Thu Jul 18 19:13:40 UTC 2013 Thierry Reding <treding@nvidia.com> ARM: tegra: Make cache line size SoC specific
Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and
therefore uses a cache line size of 64 bytes. Move the cache line size
setting to the per-SoC common configuration file.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| H A D | tegra30-common.h | 0d79f4f490352f6e1500cdd12a3b0e8b17265bde Thu Jul 18 19:13:40 UTC 2013 Thierry Reding <treding@nvidia.com> ARM: tegra: Make cache line size SoC specific
Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and
therefore uses a cache line size of 64 bytes. Move the cache line size
setting to the per-SoC common configuration file.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| H A D | tegra20-common.h | 0d79f4f490352f6e1500cdd12a3b0e8b17265bde Thu Jul 18 19:13:40 UTC 2013 Thierry Reding <treding@nvidia.com> ARM: tegra: Make cache line size SoC specific
Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and
therefore uses a cache line size of 64 bytes. Move the cache line size
setting to the per-SoC common configuration file.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| H A D | tegra-common.h | 0d79f4f490352f6e1500cdd12a3b0e8b17265bde Thu Jul 18 19:13:40 UTC 2013 Thierry Reding <treding@nvidia.com> ARM: tegra: Make cache line size SoC specific
Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and
therefore uses a cache line size of 64 bytes. Move the cache line size
setting to the per-SoC common configuration file.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|