1f01b631fSTom Warren /* 2f01b631fSTom Warren * (C) Copyright 2010-2012 3f01b631fSTom Warren * NVIDIA Corporation <www.nvidia.com> 4f01b631fSTom Warren * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6f01b631fSTom Warren */ 7f01b631fSTom Warren 8f01b631fSTom Warren #ifndef _TEGRA30_COMMON_H_ 9f01b631fSTom Warren #define _TEGRA30_COMMON_H_ 10f01b631fSTom Warren #include "tegra-common.h" 11f01b631fSTom Warren 12f01b631fSTom Warren /* 13f01b631fSTom Warren * NS16550 Configuration 14f01b631fSTom Warren */ 15f01b631fSTom Warren #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ 16f01b631fSTom Warren 17f01b631fSTom Warren /* 18f01b631fSTom Warren * Miscellaneous configurable options 19f01b631fSTom Warren */ 20f01b631fSTom Warren #define CONFIG_STACKBASE 0x82800000 /* 40MB */ 21f01b631fSTom Warren 22f01b631fSTom Warren /*----------------------------------------------------------------------- 23f01b631fSTom Warren * Physical Memory Map 24f01b631fSTom Warren */ 25*930c514dSStephen Warren #define CONFIG_SYS_TEXT_BASE 0x80110000 26f01b631fSTom Warren 27f01b631fSTom Warren /* 28f01b631fSTom Warren * Memory layout for where various images get loaded by boot scripts: 29f01b631fSTom Warren * 30f01b631fSTom Warren * scriptaddr can be pretty much anywhere that doesn't conflict with something 31f01b631fSTom Warren * else. Put it above BOOTMAPSZ to eliminate conflicts. 32f01b631fSTom Warren * 33f940c72eSStephen Warren * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 34f940c72eSStephen Warren * something else. Put it above BOOTMAPSZ to eliminate conflicts. 35f940c72eSStephen Warren * 36f01b631fSTom Warren * kernel_addr_r must be within the first 128M of RAM in order for the 37f01b631fSTom Warren * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 38f01b631fSTom Warren * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 39f01b631fSTom Warren * should not overlap that area, or the kernel will have to copy itself 40f01b631fSTom Warren * somewhere else before decompression. Similarly, the address of any other 41f01b631fSTom Warren * data passed to the kernel shouldn't overlap the start of RAM. Pushing 42f01b631fSTom Warren * this up to 16M allows for a sizable kernel to be decompressed below the 43f01b631fSTom Warren * compressed load address. 44f01b631fSTom Warren * 45f01b631fSTom Warren * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 46f01b631fSTom Warren * the compressed kernel to be up to 16M too. 47f01b631fSTom Warren * 48f01b631fSTom Warren * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 49f01b631fSTom Warren * for the FDT/DTB to be up to 1M, which is hopefully plenty. 50f01b631fSTom Warren */ 5148cfca24SStephen Warren #define CONFIG_LOADADDR 0x81000000 52f01b631fSTom Warren #define MEM_LAYOUT_ENV_SETTINGS \ 53f01b631fSTom Warren "scriptaddr=0x90000000\0" \ 54f940c72eSStephen Warren "pxefile_addr_r=0x90100000\0" \ 5548cfca24SStephen Warren "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 56f01b631fSTom Warren "fdt_addr_r=0x82000000\0" \ 57f01b631fSTom Warren "ramdisk_addr_r=0x82100000\0" 58f01b631fSTom Warren 59f01b631fSTom Warren /* Defines for SPL */ 60f01b631fSTom Warren #define CONFIG_SPL_TEXT_BASE 0x80108000 61f01b631fSTom Warren #define CONFIG_SYS_SPL_MALLOC_START 0x80090000 62f01b631fSTom Warren #define CONFIG_SPL_STACK 0x800ffffc 63f01b631fSTom Warren 64d6cf707eSJim Lin /* For USB EHCI controller */ 65d6cf707eSJim Lin #define CONFIG_EHCI_IS_TDI 6681d21e98SJim Lin #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 67d6cf707eSJim Lin 68f01b631fSTom Warren #endif /* _TEGRA30_COMMON_H_ */ 69