Searched hist:"0 c9404e1c415e0a762ad81ed7ecfe93fffbcd98a" (Results 1 – 7 of 7) sorted by relevance
| /optee_os/core/arch/arm/include/ |
| H A D | arm64_macros.S | 0c9404e1c415e0a762ad81ed7ecfe93fffbcd98a Wed Jan 26 17:54:49 UTC 2022 Jens Wiklander <jens.wiklander@linaro.org> core: panic at unexpected smc return
Certain smc's are not expected to return. Prior to this patch in order
to guard against unexpected return a "b ." instruction was added after
each such smc to at least capture the cpu. With the introduction of FF-A
TF-A may in case there's a mismatch between OP-TEE and TF-A
configuration return some error code when an unrecognized smc is
encountered. The result is typically that the boot hangs after the print:
I/TC: Primary CPU switching to normal world boot
To help diagnosing such errors a call to panic is added after
each smc which isn't expected to return. The result becomes instead:
I/TC: Primary CPU switching to normal world boot
E/TC:0 Panic at core/arch/arm/kernel/boot.c:122 <__panic_at_smc_return>
E/TC:0 TEE load address @ 0xe100000
E/TC:0 Call stack:
E/TC:0 0x0e10d23c
E/TC:0 0x0e124848
E/TC:0 0x0e10be60
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | arm32_macros.S | 0c9404e1c415e0a762ad81ed7ecfe93fffbcd98a Wed Jan 26 17:54:49 UTC 2022 Jens Wiklander <jens.wiklander@linaro.org> core: panic at unexpected smc return
Certain smc's are not expected to return. Prior to this patch in order
to guard against unexpected return a "b ." instruction was added after
each such smc to at least capture the cpu. With the introduction of FF-A
TF-A may in case there's a mismatch between OP-TEE and TF-A
configuration return some error code when an unrecognized smc is
encountered. The result is typically that the boot hangs after the print:
I/TC: Primary CPU switching to normal world boot
To help diagnosing such errors a call to panic is added after
each smc which isn't expected to return. The result becomes instead:
I/TC: Primary CPU switching to normal world boot
E/TC:0 Panic at core/arch/arm/kernel/boot.c:122 <__panic_at_smc_return>
E/TC:0 TEE load address @ 0xe100000
E/TC:0 Call stack:
E/TC:0 0x0e10d23c
E/TC:0 0x0e124848
E/TC:0 0x0e10be60
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| /optee_os/core/arch/arm/kernel/ |
| H A D | thread_optee_smc_a32.S | 0c9404e1c415e0a762ad81ed7ecfe93fffbcd98a Wed Jan 26 17:54:49 UTC 2022 Jens Wiklander <jens.wiklander@linaro.org> core: panic at unexpected smc return
Certain smc's are not expected to return. Prior to this patch in order
to guard against unexpected return a "b ." instruction was added after
each such smc to at least capture the cpu. With the introduction of FF-A
TF-A may in case there's a mismatch between OP-TEE and TF-A
configuration return some error code when an unrecognized smc is
encountered. The result is typically that the boot hangs after the print:
I/TC: Primary CPU switching to normal world boot
To help diagnosing such errors a call to panic is added after
each smc which isn't expected to return. The result becomes instead:
I/TC: Primary CPU switching to normal world boot
E/TC:0 Panic at core/arch/arm/kernel/boot.c:122 <__panic_at_smc_return>
E/TC:0 TEE load address @ 0xe100000
E/TC:0 Call stack:
E/TC:0 0x0e10d23c
E/TC:0 0x0e124848
E/TC:0 0x0e10be60
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | thread_optee_smc_a64.S | 0c9404e1c415e0a762ad81ed7ecfe93fffbcd98a Wed Jan 26 17:54:49 UTC 2022 Jens Wiklander <jens.wiklander@linaro.org> core: panic at unexpected smc return
Certain smc's are not expected to return. Prior to this patch in order
to guard against unexpected return a "b ." instruction was added after
each such smc to at least capture the cpu. With the introduction of FF-A
TF-A may in case there's a mismatch between OP-TEE and TF-A
configuration return some error code when an unrecognized smc is
encountered. The result is typically that the boot hangs after the print:
I/TC: Primary CPU switching to normal world boot
To help diagnosing such errors a call to panic is added after
each smc which isn't expected to return. The result becomes instead:
I/TC: Primary CPU switching to normal world boot
E/TC:0 Panic at core/arch/arm/kernel/boot.c:122 <__panic_at_smc_return>
E/TC:0 TEE load address @ 0xe100000
E/TC:0 Call stack:
E/TC:0 0x0e10d23c
E/TC:0 0x0e124848
E/TC:0 0x0e10be60
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | entry_a32.S | 0c9404e1c415e0a762ad81ed7ecfe93fffbcd98a Wed Jan 26 17:54:49 UTC 2022 Jens Wiklander <jens.wiklander@linaro.org> core: panic at unexpected smc return
Certain smc's are not expected to return. Prior to this patch in order
to guard against unexpected return a "b ." instruction was added after
each such smc to at least capture the cpu. With the introduction of FF-A
TF-A may in case there's a mismatch between OP-TEE and TF-A
configuration return some error code when an unrecognized smc is
encountered. The result is typically that the boot hangs after the print:
I/TC: Primary CPU switching to normal world boot
To help diagnosing such errors a call to panic is added after
each smc which isn't expected to return. The result becomes instead:
I/TC: Primary CPU switching to normal world boot
E/TC:0 Panic at core/arch/arm/kernel/boot.c:122 <__panic_at_smc_return>
E/TC:0 TEE load address @ 0xe100000
E/TC:0 Call stack:
E/TC:0 0x0e10d23c
E/TC:0 0x0e124848
E/TC:0 0x0e10be60
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | entry_a64.S | 0c9404e1c415e0a762ad81ed7ecfe93fffbcd98a Wed Jan 26 17:54:49 UTC 2022 Jens Wiklander <jens.wiklander@linaro.org> core: panic at unexpected smc return
Certain smc's are not expected to return. Prior to this patch in order
to guard against unexpected return a "b ." instruction was added after
each such smc to at least capture the cpu. With the introduction of FF-A
TF-A may in case there's a mismatch between OP-TEE and TF-A
configuration return some error code when an unrecognized smc is
encountered. The result is typically that the boot hangs after the print:
I/TC: Primary CPU switching to normal world boot
To help diagnosing such errors a call to panic is added after
each smc which isn't expected to return. The result becomes instead:
I/TC: Primary CPU switching to normal world boot
E/TC:0 Panic at core/arch/arm/kernel/boot.c:122 <__panic_at_smc_return>
E/TC:0 TEE load address @ 0xe100000
E/TC:0 Call stack:
E/TC:0 0x0e10d23c
E/TC:0 0x0e124848
E/TC:0 0x0e10be60
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | boot.c | 0c9404e1c415e0a762ad81ed7ecfe93fffbcd98a Wed Jan 26 17:54:49 UTC 2022 Jens Wiklander <jens.wiklander@linaro.org> core: panic at unexpected smc return
Certain smc's are not expected to return. Prior to this patch in order
to guard against unexpected return a "b ." instruction was added after
each such smc to at least capture the cpu. With the introduction of FF-A
TF-A may in case there's a mismatch between OP-TEE and TF-A
configuration return some error code when an unrecognized smc is
encountered. The result is typically that the boot hangs after the print:
I/TC: Primary CPU switching to normal world boot
To help diagnosing such errors a call to panic is added after
each smc which isn't expected to return. The result becomes instead:
I/TC: Primary CPU switching to normal world boot
E/TC:0 Panic at core/arch/arm/kernel/boot.c:122 <__panic_at_smc_return>
E/TC:0 TEE load address @ 0xe100000
E/TC:0 Call stack:
E/TC:0 0x0e10d23c
E/TC:0 0x0e124848
E/TC:0 0x0e10be60
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
|