Searched hist:"080939 f9244f1717c7bb4c32ff30fb72032d36fb" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/allwinner/sun50i_a64/include/ |
| H A D | sunxi_cpucfg.h | 080939f9244f1717c7bb4c32ff30fb72032d36fb Thu Jul 22 01:35:19 UTC 2021 Icenowy Zheng <icenowy@sipeed.com> refactor(plat/allwinner): allow new AA64nAA32 position
In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Cluster 0 Control Register0" in older SoCs.
Now the position of AA64nAA32 (reg and bit offset) is defined in a few
macros instead assumed to be at bit offset 24 of
SUNXI_CPUCFG_CLS_CTRL_REG0.
Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
|
| /rk3399_ARM-atf/plat/allwinner/sun50i_h616/include/ |
| H A D | sunxi_cpucfg.h | 080939f9244f1717c7bb4c32ff30fb72032d36fb Thu Jul 22 01:35:19 UTC 2021 Icenowy Zheng <icenowy@sipeed.com> refactor(plat/allwinner): allow new AA64nAA32 position
In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Cluster 0 Control Register0" in older SoCs.
Now the position of AA64nAA32 (reg and bit offset) is defined in a few
macros instead assumed to be at bit offset 24 of
SUNXI_CPUCFG_CLS_CTRL_REG0.
Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
|
| /rk3399_ARM-atf/plat/allwinner/sun50i_h6/include/ |
| H A D | sunxi_cpucfg.h | 080939f9244f1717c7bb4c32ff30fb72032d36fb Thu Jul 22 01:35:19 UTC 2021 Icenowy Zheng <icenowy@sipeed.com> refactor(plat/allwinner): allow new AA64nAA32 position
In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Cluster 0 Control Register0" in older SoCs.
Now the position of AA64nAA32 (reg and bit offset) is defined in a few
macros instead assumed to be at bit offset 24 of
SUNXI_CPUCFG_CLS_CTRL_REG0.
Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
|
| /rk3399_ARM-atf/plat/allwinner/common/ |
| H A D | sunxi_cpu_ops.c | 080939f9244f1717c7bb4c32ff30fb72032d36fb Thu Jul 22 01:35:19 UTC 2021 Icenowy Zheng <icenowy@sipeed.com> refactor(plat/allwinner): allow new AA64nAA32 position
In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Cluster 0 Control Register0" in older SoCs.
Now the position of AA64nAA32 (reg and bit offset) is defined in a few
macros instead assumed to be at bit offset 24 of
SUNXI_CPUCFG_CLS_CTRL_REG0.
Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
|