Searched hist:"00 bb8c37e0fe57ae2126857ce2d2700106a76884" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/drivers/nxp/ddr/phy-gen2/ |
| H A D | phy.h | 00bb8c37e0fe57ae2126857ce2d2700106a76884 Mon Jan 31 09:16:10 UTC 2022 Maninder Singh <maninder.singh_1@nxp.com> fix(nxp-ddr): apply Max CDD values for warm boot
Timing CFG 0 and Timing CFG 4 are ddr controller registers that
have been affected by 1d phy training during cold boot. They are
needed to be stored and restored along with phy training values.
Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I29c55256e74456515aaeb098e2e0e3475697a466
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| H A D | phy.c | 00bb8c37e0fe57ae2126857ce2d2700106a76884 Mon Jan 31 09:16:10 UTC 2022 Maninder Singh <maninder.singh_1@nxp.com> fix(nxp-ddr): apply Max CDD values for warm boot
Timing CFG 0 and Timing CFG 4 are ddr controller registers that
have been affected by 1d phy training during cold boot. They are
needed to be stored and restored along with phy training values.
Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I29c55256e74456515aaeb098e2e0e3475697a466
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