Searched hist:"00707 ccc5a0bf7f74edbd361d2aeb470047b01d8" (Results 1 – 3 of 3) sorted by relevance
| /optee_os/core/arch/arm/plat-stm32mp1/pm/ |
| H A D | psci.c | 00707ccc5a0bf7f74edbd361d2aeb470047b01d8 Mon Dec 17 16:14:27 UTC 2018 Etienne Carriere <etienne.carriere@st.com> stm32mp1: psci: implement affinity_info
This change implements PSCI_AFFINITY_INFO for platform stm32mp1.
The cores state are saved in a local array and accessed with SMP
locking protection. Note these do not lock/unlock if executed with
the MMU disabled.
CPU shall call stm32mp_register_online_cpu() when online in the
secure world. GIC CPU interface initialization is used to register
online primary and secondary boot cores.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| /optee_os/core/arch/arm/plat-stm32mp1/ |
| H A D | stm32_util.h | 00707ccc5a0bf7f74edbd361d2aeb470047b01d8 Mon Dec 17 16:14:27 UTC 2018 Etienne Carriere <etienne.carriere@st.com> stm32mp1: psci: implement affinity_info
This change implements PSCI_AFFINITY_INFO for platform stm32mp1.
The cores state are saved in a local array and accessed with SMP
locking protection. Note these do not lock/unlock if executed with
the MMU disabled.
CPU shall call stm32mp_register_online_cpu() when online in the
secure world. GIC CPU interface initialization is used to register
online primary and secondary boot cores.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| H A D | main.c | 00707ccc5a0bf7f74edbd361d2aeb470047b01d8 Mon Dec 17 16:14:27 UTC 2018 Etienne Carriere <etienne.carriere@st.com> stm32mp1: psci: implement affinity_info
This change implements PSCI_AFFINITY_INFO for platform stm32mp1.
The cores state are saved in a local array and accessed with SMP
locking protection. Note these do not lock/unlock if executed with
the MMU disabled.
CPU shall call stm32mp_register_online_cpu() when online in the
secure world. GIC CPU interface initialization is used to register
online primary and secondary boot cores.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
|