Searched +full:uniphier +full:- +full:pro4 +full:- +full:soc +full:- +full:glue (Results 1 – 8 of 8) sorted by relevance
1 UniPhier glue reset controller4 Peripheral core reset in glue layer5 -----------------------------------7 Some peripheral core reset belongs to its own glue layer. Before using12 - compatible: Should be13 "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB314 "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB315 "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB316 "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB317 "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3[all …]
1 Socionext UniPhier Regulator Controller4 on Socionext UniPhier SoCs.7 ---------------9 This regulator controls VBUS and belongs to USB3 glue layer. Before using14 - compatible: Should be15 "socionext,uniphier-pro4-usb3-regulator" - for Pro4 SoC16 "socionext,uniphier-pro5-usb3-regulator" - for Pro5 SoC17 "socionext,uniphier-pxs2-usb3-regulator" - for PXs2 SoC18 "socionext,uniphier-ld20-usb3-regulator" - for LD20 SoC19 "socionext,uniphier-pxs3-usb3-regulator" - for PXs3 SoC[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT3 // Device Tree Source for UniPhier Pro4 SoC5 // Copyright (C) 2015-2016 Socionext Inc.8 #include <dt-bindings/gpio/uniphier-gpio.h>11 compatible = "socionext,uniphier-pro4";12 #address-cells = <1>;13 #size-cells = <1>;16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a9";[all …]
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/pinctrl/socionext,uniphier-pinctrl.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: UniPhier SoCs pin controller10 - Masahiro Yamada <yamada.masahiro@socionext.com>18 - socionext,uniphier-ld4-pinctrl19 - socionext,uniphier-pro4-pinctrl20 - socionext,uniphier-sld8-pinctrl21 - socionext,uniphier-pro5-pinctrl[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Socionext UniPhier USB2 PHY11 USB2 controller implemented on Socionext UniPhier SoCs.12 Pro4 SoC has both USB2 and USB3 host controllers, however, this USB313 controller doesn't include its own High-Speed PHY. This needs to specify14 USB2 PHY instead of USB3 HS-PHY.17 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>[all …]
2 * Device Tree Source for UniPhier Pro4 SoC4 * Copyright (C) 2015-2016 Socionext Inc.7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)11 compatible = "socionext,uniphier-pro4";12 #address-cells = <1>;13 #size-cells = <1>;16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a9";23 enable-method = "psci";[all …]
2 * UniPhier SG (SoC Glue) block registers4 * Copyright (C) 2011-2015 Copyright (C) 2011-2015 Panasonic Corporation5 * Copyright (C) 2016-2017 Socionext Inc.8 * SPDX-License-Identifier: GPL-2.0+53 /* PH1-LD6b, ProXstream2, PH1-LD20 only */65 /* PH1-Pro4, PH1-Pro5 */96 and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))111 u32 mask = (1U << mux_bits) - 1; in sg_set_pinsel()
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