1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * UniPhier SG (SoC Glue) block registers
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2011-2015 Copyright (C) 2011-2015 Panasonic Corporation
5*4882a593Smuzhiyun * Copyright (C) 2016-2017 Socionext Inc.
6*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #ifndef UNIPHIER_SG_REGS_H
12*4882a593Smuzhiyun #define UNIPHIER_SG_REGS_H
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /* Base Address */
15*4882a593Smuzhiyun #define SG_CTRL_BASE 0x5f800000
16*4882a593Smuzhiyun #define SG_DBG_BASE 0x5f900000
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* Revision */
19*4882a593Smuzhiyun #define SG_REVISION (SG_CTRL_BASE | 0x0000)
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* Memory Configuration */
22*4882a593Smuzhiyun #define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
25*4882a593Smuzhiyun #define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
26*4882a593Smuzhiyun #define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
27*4882a593Smuzhiyun #define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
28*4882a593Smuzhiyun #define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
29*4882a593Smuzhiyun #define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
30*4882a593Smuzhiyun #define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
31*4882a593Smuzhiyun #define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
32*4882a593Smuzhiyun #define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
35*4882a593Smuzhiyun #define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
36*4882a593Smuzhiyun #define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
37*4882a593Smuzhiyun #define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
38*4882a593Smuzhiyun #define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
39*4882a593Smuzhiyun #define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
40*4882a593Smuzhiyun #define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
41*4882a593Smuzhiyun #define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
42*4882a593Smuzhiyun #define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
45*4882a593Smuzhiyun #define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
46*4882a593Smuzhiyun #define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
47*4882a593Smuzhiyun #define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
48*4882a593Smuzhiyun #define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
49*4882a593Smuzhiyun #define SG_MEMCONF_CH2_SZ_1G ((0x1 << 26) | (0x01 << 16))
50*4882a593Smuzhiyun #define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
51*4882a593Smuzhiyun #define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
52*4882a593Smuzhiyun #define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
53*4882a593Smuzhiyun /* PH1-LD6b, ProXstream2, PH1-LD20 only */
54*4882a593Smuzhiyun #define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define SG_MEMCONF_SPARSEMEM (0x1 << 4)
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define SG_USBPHYCTRL (SG_CTRL_BASE | 0x500)
59*4882a593Smuzhiyun #define SG_ETPHYPSHUT (SG_CTRL_BASE | 0x554)
60*4882a593Smuzhiyun #define SG_ETPHYCNT (SG_CTRL_BASE | 0x550)
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Pin Control */
63*4882a593Smuzhiyun #define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* PH1-Pro4, PH1-Pro5 */
66*4882a593Smuzhiyun #define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* Input Enable */
69*4882a593Smuzhiyun #define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* Pin Monitor */
72*4882a593Smuzhiyun #define SG_PINMON0 (SG_DBG_BASE | 0x0100)
73*4882a593Smuzhiyun #define SG_PINMON2 (SG_DBG_BASE | 0x0108)
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
76*4882a593Smuzhiyun #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
77*4882a593Smuzhiyun #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
78*4882a593Smuzhiyun #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun #define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
81*4882a593Smuzhiyun #define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
82*4882a593Smuzhiyun #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
83*4882a593Smuzhiyun #define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
84*4882a593Smuzhiyun #define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
87*4882a593Smuzhiyun #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
88*4882a593Smuzhiyun #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
89*4882a593Smuzhiyun #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #ifdef __ASSEMBLY__
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
94*4882a593Smuzhiyun ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
95*4882a593Smuzhiyun ldr \rd, [\ra]
96*4882a593Smuzhiyun and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
97*4882a593Smuzhiyun orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
98*4882a593Smuzhiyun str \rd, [\ra]
99*4882a593Smuzhiyun .endm
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #else
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #include <linux/types.h>
104*4882a593Smuzhiyun #include <linux/io.h>
105*4882a593Smuzhiyun
sg_set_pinsel(unsigned pin,unsigned muxval,unsigned mux_bits,unsigned reg_stride)106*4882a593Smuzhiyun static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
107*4882a593Smuzhiyun unsigned mux_bits, unsigned reg_stride)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun unsigned shift = pin * mux_bits % 32;
110*4882a593Smuzhiyun unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
111*4882a593Smuzhiyun u32 mask = (1U << mux_bits) - 1;
112*4882a593Smuzhiyun u32 tmp;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun tmp = readl(reg);
115*4882a593Smuzhiyun tmp &= ~(mask << shift);
116*4882a593Smuzhiyun tmp |= (mask & muxval) << shift;
117*4882a593Smuzhiyun writel(tmp, reg);
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
sg_set_iectrl(unsigned pin)120*4882a593Smuzhiyun static inline void sg_set_iectrl(unsigned pin)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun unsigned bit = pin % 32;
123*4882a593Smuzhiyun unsigned long reg = SG_IECTRL + pin / 32 * 4;
124*4882a593Smuzhiyun u32 tmp;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun tmp = readl(reg);
127*4882a593Smuzhiyun tmp |= 1 << bit;
128*4882a593Smuzhiyun writel(tmp, reg);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
sg_set_iectrl_range(unsigned min,unsigned max)131*4882a593Smuzhiyun static inline void sg_set_iectrl_range(unsigned min, unsigned max)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun int i;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun for (i = min; i <= max; i++)
136*4882a593Smuzhiyun sg_set_iectrl(i);
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun #endif /* UNIPHIER_SG_REGS_H */
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