Searched +full:j721e +full:- +full:usb (Results 1 – 13 of 13) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#"5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"7 title: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller10 - Roger Quadros <rogerq@ti.com>15 - const: ti,j721e-usb20 power-domains:23 the USB device id value. See,24 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/10 compatible = "mmio-sram";12 #address-cells = <1>;13 #size-cells = <1>;16 atf-sram@0 {21 scm_conf: scm-conf@100000 {22 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";24 #address-cells = <1>;25 #size-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for J721E SoC Family Main Domain peripherals5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/7 #include <dt-bindings/phy/phy.h>8 #include <dt-bindings/mux/mux.h>9 #include <dt-bindings/mux/ti-serdes.h>12 cmn_refclk: clock-cmnrefclk {13 #clock-cells = <0>;14 compatible = "fixed-clock";15 clock-frequency = <0>;[all …]
1 # SPDX-License-Identifier: GPL-2.0-only6 tristate "TI DA8xx USB PHY Driver"11 Enable this to support the USB PHY on DA8xx SoCs.13 This driver controls both the USB 1.1 PHY and the USB 2.0 PHY.16 tristate "TI dm816x USB PHY driver"22 Enable this for dm816x USB to work.37 tristate "TI J721E WIZ (SERDES Wrapper) support"46 This option enables support for WIZ module present in TI's J721E73 The USB OTG controller communicates with the comparator using this92 Support for TI TUSB1210 USB ULPI PHY.[all …]
1 # SPDX-License-Identifier: GPL-2.02 obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o3 obj-$(CONFIG_PHY_DM816X_USB) += phy-dm816x-usb.o4 obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o5 obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o6 obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o7 obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o8 obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o9 obj-$(CONFIG_PHY_AM654_SERDES) += phy-am654-serdes.o10 obj-$(CONFIG_PHY_TI_GMII_SEL) += phy-gmii-sel.o[all …]
2 tristate "Cadence USB3 Dual-Role Controller"3 depends on USB_SUPPORT && (USB || USB_GADGET) && HAS_DMA7 Say Y here if your system has a Cadence USB3 dual-role controller.8 It supports: dual-role switch, Host-only, and Peripheral-only.20 Cadence USBSS-DEV driver.27 depends on USB=y || USB=USB_CDNS336 tristate "Cadence USB3 support on PCIe-based platforms"44 be dynamically linked and module will be called cdns3-pci.ko54 e.g. J721e.
1 // SPDX-License-Identifier: GPL-2.03 * cdns3-ti.c - TI specific Glue layer for Cadence USB Controller5 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com14 #include <linux/dma-mapping.h>19 /* USB Wrapper register offsets */79 return readl(data->usbss + offset); in cdns_ti_readl()84 writel(value, data->usbss + offset); in cdns_ti_writel()89 struct device *dev = &pdev->dev; in cdns_ti_probe()90 struct device_node *node = pdev->dev.of_node; in cdns_ti_probe()99 return -ENOMEM; in cdns_ti_probe()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only12 is currently used by the USB driver on AM335x and DA8xx platforms.27 tristate "Texas Instruments sDMA (omap-dma) support"48 DMA engine is used in AM65x and j721e.
1 // SPDX-License-Identifier: GPL-2.03 * cdns_ti-ti.c - TI specific Glue layer for Cadence USB Controller5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com9 #include <asm-generic/io.h>13 #include <linux/usb/otg.h>18 /* USB Wrapper register offsets */78 return readl(data->usbss + offset); in cdns_ti_readl()83 writel(value, data->usbss + offset); in cdns_ti_writel()96 data->dev = dev; in cdns_ti_probe()98 data->usbss = dev_remap_addr_index(dev, 0); in cdns_ti_probe()[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"13 such as PCIe, USB, SGMII, QSGMII etc.16 - Swapnil Jakhade <sjakhade@cadence.com>17 - Yuti Amonkar <yamonkar@cadence.com>22 - cdns,torrent-phy23 - ti,j721e-serdes-10g25 '#address-cells':[all …]
... -boot-2021.07/.readthedocs.yml u-boot-2021.07/Kbuild u-boot-2021.07 ...
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 #include <dt-bindings/phy/phy.h>365 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_write()367 writew(val, ctx->base + offset); in cdns_regmap_write()375 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_read()377 *val = readw(ctx->base + offset); in cdns_regmap_read()387 writel(val, ctx->base + offset); in cdns_regmap_dptx_write()398 *val = readl(ctx->base + offset); in cdns_regmap_dptx_read()497 * Structure used to store values of PHY registers for voltage-related498 * coefficients, for particular voltage swing and pre-emphasis level. Values[all …]