Searched +full:j721e +full:- +full:pcie +full:- +full:host (Results 1 – 11 of 11) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 menu "Cadence PCIe controllers support"25 bool "Cadence PCIe platform host controller"30 Say Y here if you want to support the Cadence PCIe platform controller in31 host mode. This PCIe controller may be embedded into many different35 bool "Cadence PCIe platform endpoint controller"41 Say Y here if you want to support the Cadence PCIe platform controller in42 endpoint mode. This PCIe controller may be embedded into many49 bool "TI J721E PCIe platform host controller"54 Say Y here if you want to support the TI J721E PCIe platform[all …]
1 // SPDX-License-Identifier: GPL-2.03 * pci-j721e - PCIe controller driver for TI's J721E SoCs5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com22 #include "pcie-cadence.h"74 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_user_readl() argument76 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()79 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_user_writel() argument82 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()85 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_intd_readl() argument87 return readl(pcie->intd_cfg_base + offset); in j721e_pcie_intd_readl()[all …]
1 # SPDX-License-Identifier: GPL-2.02 obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o3 obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o4 obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o5 obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o6 obj-$(CONFIG_PCI_J721E) += pci-j721e.o
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/4 ---5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"8 title: TI J721E PCI Host (PCIe Wrapper)11 - Kishon Vijay Abraham I <kishon@ti.com>14 - $ref: "cdns-pcie-host.yaml#"19 - ti,j721e-pcie-host24 reg-names:[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for J721E SoC Family Main Domain peripherals5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/7 #include <dt-bindings/phy/phy.h>8 #include <dt-bindings/mux/mux.h>9 #include <dt-bindings/mux/ti-serdes.h>12 cmn_refclk: clock-cmnrefclk {13 #clock-cells = <0>;14 compatible = "fixed-clock";15 clock-frequency = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/6 /dts-v1/;8 #include "k3-j721e-som-p0.dtsi"9 #include <dt-bindings/gpio/gpio.h>10 #include <dt-bindings/input/input.h>11 #include <dt-bindings/net/ti-dp83867.h>15 stdout-path = "serial2:115200n8";19 gpio_keys: gpio-keys {20 compatible = "gpio-keys";[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpts.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: The TI AM654x/J721E Common Platform Time Sync (CPTS) module Device Tree Bindings10 - Grygorii Strashko <grygorii.strashko@ti.com>11 - Sekhar Nori <nsekhar@ti.com>14 The TI AM654x/J721E CPTS module is used to facilitate host control of time17 - selection of multiple external clock sources18 - Software control of time sync events via interrupt or polling[all …]
1 # SPDX-License-Identifier: GPL-2.0-only34 PCIe.37 tristate "TI J721E WIZ (SERDES Wrapper) support"46 This option enables support for WIZ module present in TI's J721E60 additional register to power on USB3 PHY/SATA PHY/PCIE PHY105 in host mode, low speed.
2 tristate "Cadence USB3 Dual-Role Controller"7 Say Y here if your system has a Cadence USB3 dual-role controller.8 It supports: dual-role switch, Host-only, and Peripheral-only.20 Cadence USBSS-DEV driver.26 bool "Cadence USB3 host controller"29 Say Y here to enable host controller functionality of the32 Host controller is compliant with XHCI so it will use36 tristate "Cadence USB3 support on PCIe-based platforms"40 If you're using the USBSS Core IP with a PCIe, please say44 be dynamically linked and module will be called cdns3-pci.ko[all …]
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]
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