Searched +full:exynos5420 +full:- +full:i2s (Results 1 – 12 of 12) sorted by relevance
9 - compatible: should be one of the following:10 - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.11 - "samsung,exynos5250-audss-clock" - controller compatible with Exynos525013 - "samsung,exynos5410-audss-clock" - controller compatible with Exynos541015 - "samsung,exynos5420-audss-clock" - controller compatible with Exynos542017 - reg: physical base address and length of the controller's register set.19 - #clock-cells: should be 1.21 - clocks:22 - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"24 - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Samsung SoC I2S controller10 - Krzysztof Kozlowski <krzk@kernel.org>11 - Sylwester Nawrocki <s.nawrocki@samsung.com>16 samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.18 samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with22 samsung,exynos5420-i2s: for 8/16/24bit multichannel (5.1) I2S for[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Samsung Exynos5420 SoC device tree source8 * Samsung Exynos5420 SoC device nodes are listed in this file.9 * Exynos5420 based board files can include this file and provide14 #include <dt-bindings/clock/exynos5420.h>15 #include <dt-bindings/clock/exynos-audss-clk.h>16 #include <dt-bindings/interrupt-controller/arm-gic.h>19 compatible = "samsung,exynos5420", "samsung,exynos5";42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.46 compatible = "operating-points-v2";[all …]
1 // SPDX-License-Identifier: GPL-2.014 #include <dt-bindings/clock/exynos5410.h>15 #include <dt-bindings/clock/exynos-audss-clk.h>16 #include <dt-bindings/interrupt-controller/arm-gic.h>20 interrupt-parent = <&gic>;30 #address-cells = <1>;31 #size-cells = <0>;35 compatible = "arm,cortex-a15";37 clock-frequency = <1600000000>;42 compatible = "arm,cortex-a15";[all …]
1 // SPDX-License-Identifier: GPL-2.08 /dts-v1/;9 #include <dt-bindings/input/input.h>10 #include <dt-bindings/gpio/gpio.h>11 #include <dt-bindings/interrupt-controller/irq.h>12 #include <dt-bindings/clock/maxim,max77802.h>13 #include <dt-bindings/regulator/maxim,max77802.h>14 #include <dt-bindings/sound/samsung-i2s.h>15 #include "exynos5420.dtsi"16 #include "exynos5420-cpus.dtsi"[all …]
1 // SPDX-License-Identifier: GPL-2.08 /dts-v1/;9 #include <dt-bindings/input/input.h>10 #include <dt-bindings/gpio/gpio.h>11 #include <dt-bindings/interrupt-controller/irq.h>12 #include <dt-bindings/clock/maxim,max77802.h>13 #include <dt-bindings/regulator/maxim,max77802.h>14 #include <dt-bindings/sound/samsung-i2s.h>16 #include "exynos5420-cpus.dtsi"21 compatible = "google,pi-rev16",[all …]
1 // SPDX-License-Identifier: GPL-2.017 #include "exynos4-cpu-thermal.dtsi"18 #include <dt-bindings/clock/exynos3250.h>19 #include <dt-bindings/interrupt-controller/arm-gic.h>20 #include <dt-bindings/interrupt-controller/irq.h>24 interrupt-parent = <&gic>;25 #address-cells = <1>;26 #size-cells = <1>;50 #address-cells = <1>;51 #size-cells = <0>;[all …]
5 * SPDX-License-Identifier: GPL-2.0+149 /* EXYNOS5420 */232 /* Exynos5420 */ in s5p_set_cpu_id()237 * Exynos5800 is a variant of Exynos5420 in s5p_set_cpu_id()269 IS_EXYNOS_TYPE(exynos5420, 0x5420)293 SAMSUNG_BASE(i2s, I2S_BASE)
1 // SPDX-License-Identifier: GPL-2.03 // ALSA SoC Audio Layer - Samsung I2S Controller driver8 #include <dt-bindings/sound/samsung-i2s.h>12 #include <linux/clk-provider.h>23 #include <linux/platform_data/asoc-s3c.h>27 #include "i2s.h"28 #include "i2s-regs.h"99 /* The I2S controller's core clock */102 /* Clock for generating I2S signals */108 /* Cache of selected I2S registers for system suspend */[all …]
1 // SPDX-License-Identifier: GPL-2.0-only7 * Common Clock Framework support for Exynos5420 SoC.10 #include <dt-bindings/clock/exynos5420.h>12 #include <linux/clk-provider.h>18 #include "clk-cpu.h"19 #include "clk-exynos5-subcmu.h"144 EXYNOS5420, enumerator894 /* Audio - I2S */901 /* SPI Pre-Ratio */1435 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later5 * Seung-Woo Kim <sw0312.kim@samsung.com>9 * Based on drivers/media/video/s5p-tv/hdmi_drv.c33 #include <sound/hdmi-codec.h>34 #include <media/cec-notifier.h>44 #include "regs-hdmi.h"105 * required parents of clock when HDMI-PHY is respectively off or on.671 return hdmi_reg_map[reg_id & 0xffff][hdata->drv_data->type]; in hdmi_map_reg()677 return readl(hdata->regs + hdmi_map_reg(hdata, reg_id)); in hdmi_reg_read()683 writel(value, hdata->regs + hdmi_map_reg(hdata, reg_id)); in hdmi_reg_writeb()[all …]
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