xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/samsung-i2s.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Samsung SoC I2S controller
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Krzysztof Kozlowski <krzk@kernel.org>
11*4882a593Smuzhiyun  - Sylwester Nawrocki <s.nawrocki@samsung.com>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyunproperties:
14*4882a593Smuzhiyun  compatible:
15*4882a593Smuzhiyun    description: |
16*4882a593Smuzhiyun      samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun      samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with
19*4882a593Smuzhiyun      secondary FIFO, s/w reset control and internal mux for root clock
20*4882a593Smuzhiyun      source.
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun      samsung,exynos5420-i2s: for 8/16/24bit multichannel (5.1) I2S for
23*4882a593Smuzhiyun      playback, stereo channel capture, secondary FIFO using internal
24*4882a593Smuzhiyun      or external DMA, s/w reset control, internal mux for root clock
25*4882a593Smuzhiyun      source and 7.1 channel TDM support for playback; TDM (Time division
26*4882a593Smuzhiyun      multiplexing) is to allow transfer of multiple channel audio data on
27*4882a593Smuzhiyun      single data line.
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun      samsung,exynos7-i2s: with all the available features of Exynos5 I2S.
30*4882a593Smuzhiyun      Exynos7 I2S has 7.1 channel TDM support for capture, secondary FIFO
31*4882a593Smuzhiyun      with only external DMA and more number of root clock sampling
32*4882a593Smuzhiyun      frequencies.
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun      samsung,exynos7-i2s1: I2S1 on previous samsung platforms supports
35*4882a593Smuzhiyun      stereo channels. Exynos7 I2S1 upgraded to 5.1 multichannel with
36*4882a593Smuzhiyun      slightly modified bit offsets.
37*4882a593Smuzhiyun    enum:
38*4882a593Smuzhiyun      - samsung,s3c6410-i2s
39*4882a593Smuzhiyun      - samsung,s5pv210-i2s
40*4882a593Smuzhiyun      - samsung,exynos5420-i2s
41*4882a593Smuzhiyun      - samsung,exynos7-i2s
42*4882a593Smuzhiyun      - samsung,exynos7-i2s1
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun  '#address-cells':
45*4882a593Smuzhiyun    const: 1
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun  '#size-cells':
48*4882a593Smuzhiyun    const: 0
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun  reg:
51*4882a593Smuzhiyun    maxItems: 1
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun  dmas:
54*4882a593Smuzhiyun    minItems: 2
55*4882a593Smuzhiyun    maxItems: 3
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun  dma-names:
58*4882a593Smuzhiyun    oneOf:
59*4882a593Smuzhiyun      - items:
60*4882a593Smuzhiyun          - const: tx
61*4882a593Smuzhiyun          - const: rx
62*4882a593Smuzhiyun      - items:
63*4882a593Smuzhiyun          - const: tx
64*4882a593Smuzhiyun          - const: rx
65*4882a593Smuzhiyun          - const: tx-sec
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun  assigned-clock-parents: true
68*4882a593Smuzhiyun  assigned-clocks: true
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun  clocks:
71*4882a593Smuzhiyun    minItems: 1
72*4882a593Smuzhiyun    maxItems: 3
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun  clock-names:
75*4882a593Smuzhiyun    oneOf:
76*4882a593Smuzhiyun      - items:
77*4882a593Smuzhiyun          - const: iis
78*4882a593Smuzhiyun      - items: # for I2S0
79*4882a593Smuzhiyun          - const: iis
80*4882a593Smuzhiyun          - const: i2s_opclk0
81*4882a593Smuzhiyun          - const: i2s_opclk1
82*4882a593Smuzhiyun      - items: # for I2S1 and I2S2
83*4882a593Smuzhiyun          - const: iis
84*4882a593Smuzhiyun          - const: i2s_opclk0
85*4882a593Smuzhiyun    description: |
86*4882a593Smuzhiyun      "iis" is the I2S bus clock and i2s_opclk0, i2s_opclk1 are sources
87*4882a593Smuzhiyun      of the root clock. I2S0 has internal mux to select the source
88*4882a593Smuzhiyun      of root clock and I2S1 and I2S2 doesn't have any such mux.
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun  "#clock-cells":
91*4882a593Smuzhiyun    const: 1
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun  clock-output-names:
94*4882a593Smuzhiyun    deprecated: true
95*4882a593Smuzhiyun    oneOf:
96*4882a593Smuzhiyun      - items: # for I2S0
97*4882a593Smuzhiyun          - const: i2s_cdclk0
98*4882a593Smuzhiyun      - items: # for I2S1
99*4882a593Smuzhiyun          - const: i2s_cdclk1
100*4882a593Smuzhiyun      - items: # for I2S2
101*4882a593Smuzhiyun          - const: i2s_cdclk2
102*4882a593Smuzhiyun    description: Names of the CDCLK I2S output clocks.
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun  interrupts:
105*4882a593Smuzhiyun    maxItems: 1
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun  samsung,idma-addr:
108*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
109*4882a593Smuzhiyun    description: |
110*4882a593Smuzhiyun      Internal DMA register base address of the audio
111*4882a593Smuzhiyun      subsystem (used in secondary sound source).
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun  pinctrl-0:
114*4882a593Smuzhiyun    description: Should specify pin control groups used for this controller.
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun  pinctrl-names:
117*4882a593Smuzhiyun    const: default
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun  power-domains:
120*4882a593Smuzhiyun    maxItems: 1
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun  "#sound-dai-cells":
123*4882a593Smuzhiyun    const: 1
124*4882a593Smuzhiyun
125*4882a593Smuzhiyunrequired:
126*4882a593Smuzhiyun  - compatible
127*4882a593Smuzhiyun  - reg
128*4882a593Smuzhiyun  - dmas
129*4882a593Smuzhiyun  - dma-names
130*4882a593Smuzhiyun  - clocks
131*4882a593Smuzhiyun  - clock-names
132*4882a593Smuzhiyun
133*4882a593SmuzhiyunadditionalProperties: false
134*4882a593Smuzhiyun
135*4882a593Smuzhiyunexamples:
136*4882a593Smuzhiyun  - |
137*4882a593Smuzhiyun    #include <dt-bindings/clock/exynos-audss-clk.h>
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun    i2s0: i2s@3830000 {
140*4882a593Smuzhiyun        compatible = "samsung,s5pv210-i2s";
141*4882a593Smuzhiyun        reg = <0x03830000 0x100>;
142*4882a593Smuzhiyun        dmas = <&pdma0 10>,
143*4882a593Smuzhiyun                <&pdma0 9>,
144*4882a593Smuzhiyun                <&pdma0 8>;
145*4882a593Smuzhiyun        dma-names = "tx", "rx", "tx-sec";
146*4882a593Smuzhiyun        clocks = <&clock_audss EXYNOS_I2S_BUS>,
147*4882a593Smuzhiyun                <&clock_audss EXYNOS_I2S_BUS>,
148*4882a593Smuzhiyun                <&clock_audss EXYNOS_SCLK_I2S>;
149*4882a593Smuzhiyun        clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
150*4882a593Smuzhiyun        #clock-cells = <1>;
151*4882a593Smuzhiyun        samsung,idma-addr = <0x03000000>;
152*4882a593Smuzhiyun        pinctrl-names = "default";
153*4882a593Smuzhiyun        pinctrl-0 = <&i2s0_bus>;
154*4882a593Smuzhiyun        #sound-dai-cells = <1>;
155*4882a593Smuzhiyun    };
156