Searched +full:exynos5250 +full:- +full:wdt (Results 1 – 8 of 8) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/watchdog/samsung-wdt.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Krzysztof Kozlowski <krzk@kernel.org>14 after a preset amount of time during which the WDT reset event has not20 - samsung,s3c2410-wdt # for S3C241021 - samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos422 - samsung,exynos5250-wdt # for Exynos525023 - samsung,exynos5420-wdt # for Exynos5420[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.28 arm_a7_pmu: arm-a7-pmu {29 compatible = "arm,cortex-a7-pmu";30 interrupt-parent = <&gic>;38 arm_a15_pmu: arm-a15-pmu {39 compatible = "arm,cortex-a15-pmu";40 interrupt-parent = <&combiner>;49 compatible = "arm,armv7-timer";54 clock-frequency = <24000000>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Samsung Exynos5250 SoC device tree source8 * Samsung Exynos5250 SoC device nodes are listed in this file.9 * Exynos5250 based board files can include this file and provide13 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,17 #include <dt-bindings/clock/exynos5250.h>19 #include "exynos4-cpu-thermal.dtsi"20 #include <dt-bindings/clock/exynos-audss-clk.h>23 compatible = "samsung,exynos5250", "samsung,exynos5";50 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.019 #include "exynos4-cpu-thermal.dtsi"29 fimc-lite0 = &fimc_lite_0;30 fimc-lite1 = &fimc_lite_1;35 #address-cells = <1>;36 #size-cells = <0>;40 compatible = "arm,cortex-a9";43 clock-names = "cpu";44 operating-points-v2 = <&cpu0_opp_table>;45 #cooling-cells = <2>; /* min followed by max */[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later87 * struct s3c2410_wdt_variant - Per-variant config data164 { .compatible = "samsung,s3c2410-wdt",166 { .compatible = "samsung,s3c6410-wdt",168 { .compatible = "samsung,exynos5250-wdt",170 { .compatible = "samsung,exynos5420-wdt",172 { .compatible = "samsung,exynos7-wdt",181 .name = "s3c2410-wdt",203 static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) in s3c2410wdt_mask_and_disable_reset() argument206 u32 mask_val = 1 << wdt->drv_data->mask_bit; in s3c2410wdt_mask_and_disable_reset()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only7 * Common Clock Framework support for Exynos5250 SoC.10 #include <dt-bindings/clock/exynos5250.h>11 #include <linux/clk-provider.h>17 #include "clk-cpu.h"18 #include "clk-exynos5-subcmu.h"626 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),776 { .compatible = "samsung,clock-xxti", .data = (void *)0, },796 hws = ctx->clk_data.hws; in exynos5250_clk_init()857 pr_info("Exynos5250: clock setup completed, armclk=%ld\n", in exynos5250_clk_init()[all …]
... -boot-2021.07/.readthedocs.yml u-boot-2021.07/Kbuild u-boot-2021.07 ...
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]