Searched +full:bt1 +full:- +full:axi (Results 1 – 12 of 12) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Baikal-T1 Clock Control Unit Dividers11 - Serge Semin <fancer.lancer@gmail.com>14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller18 IP-blocks or to groups of blocks (clock domains). The transformation is done19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The22 registers. Baikal-T1 CCU is logically divided into the next components:[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Baikal-T1 Clock Control Unit PLL11 - Serge Semin <fancer.lancer@gmail.com>14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller18 IP-blocks or to groups of blocks (clock domains). The transformation is done19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.23 2) PLLs clocks generators (PLLs) - described in this binding file.[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Baikal-T1 AXI-bus11 - Serge Semin <fancer.lancer@gmail.com>14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all15 high-speed peripheral IP-cores with RAM controller and with MIPS P560016 cores. Traffic arbitration is done by means of DW AXI Interconnect (so17 called AXI Main Interconnect) routing IO requests from one block to[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Baikal-T1 APB-bus11 - Serge Semin <fancer.lancer@gmail.com>14 Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect15 which routes them to the AXI-APB bridge. This interface is a single master22 - $ref: /schemas/simple-bus.yaml#27 const: baikal,bt1-apb[all …]
1 // SPDX-License-Identifier: GPL-2.0-only8 * Baikal-T1 AXI-bus driver35 * struct bt1_axi - Baikal-T1 AXI-bus private data37 * @qos_regs: AXI Interconnect QoS tuning registers.38 * @sys_regs: Baikal-T1 System Controller registers map.40 * @aclk: AXI reference clock.41 * @arst: AXI Interconnect reset line.60 struct bt1_axi *axi = data; in bt1_axi_isr() local63 regmap_read(axi->sys_regs, BT1_AXI_WERRL, &low); in bt1_axi_isr()64 regmap_read(axi->sys_regs, BT1_AXI_WERRH, &high); in bt1_axi_isr()[all …]
1 # SPDX-License-Identifier: GPL-2.07 obj-$(CONFIG_ARM_CCI) += arm-cci.o8 obj-$(CONFIG_ARM_INTEGRATOR_LM) += arm-integrator-lm.o9 obj-$(CONFIG_HISILICON_LPC) += hisi_lpc.o10 obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o11 obj-$(CONFIG_MOXTET) += moxtet.o13 # DPAA2 fsl-mc bus14 obj-$(CONFIG_FSL_MC_BUS) += fsl-mc/16 obj-$(CONFIG_BT1_APB) += bt1-apb.o17 obj-$(CONFIG_BT1_AXI) += bt1-axi.o[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 * Baikal-T1 CCU Dividers clock driver12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt17 #include <linux/clk-provider.h>18 #include <linux/reset-controller.h>26 #include <dt-bindings/clock/bt1-ccu.h>27 #include <dt-bindings/reset/bt1-ccu.h>29 #include "ccu-div.h"138 * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks141 * the later is clocking the AXI-bus between DDR controller and the Main[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 * Baikal-T1 CCU PLL clocks driver12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt17 #include <linux/clk-provider.h>24 #include <dt-bindings/clock/bt1-ccu.h>26 #include "ccu-pll.h"56 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and57 * DDR controller AXI-bus clocks. If they are gated the system will be59 * of the corresponding subsystems. So until we aren't ready to re-initialize88 pll = data->plls[idx]; in ccu_pll_find_desc()[all …]
1 # SPDX-License-Identifier: GPL-2.06 ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG8 # small core, mostly translating board-specific10 obj-$(CONFIG_SPI_MASTER) += spi.o11 obj-$(CONFIG_SPI_MEM) += spi-mem.o12 obj-$(CONFIG_SPI_MUX) += spi-mux.o13 obj-$(CONFIG_SPI_SPIDEV) += spidev.o14 obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o17 obj-$(CONFIG_SPI_ALTERA) += spi-altera.o18 obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o[all …]
1 # SPDX-License-Identifier: GPL-2.06 obj-$(CONFIG_HWMON) += hwmon.o7 obj-$(CONFIG_HWMON_VID) += hwmon-vid.o10 obj-$(CONFIG_SENSORS_ACPI_POWER) += acpi_power_meter.o11 obj-$(CONFIG_SENSORS_ATK0110) += asus_atk0110.o15 obj-$(CONFIG_SENSORS_ASB100) += asb100.o16 obj-$(CONFIG_SENSORS_W83627HF) += w83627hf.o17 obj-$(CONFIG_SENSORS_W83773G) += w83773g.o18 obj-$(CONFIG_SENSORS_W83792D) += w83792d.o19 obj-$(CONFIG_SENSORS_W83793) += w83793.o[all …]
1 # SPDX-License-Identifier: GPL-2.0-only20 sensors-detect script from the lm_sensors package. Read21 <file:Documentation/hwmon/userspace-tools.rst> for details.52 will be called abx500-temp.267 will be called as370-hwmon.287 AXI HDL FAN monitoring core.290 will be called axi-fan-control299 lm-sensors 2.10.1 for proper userspace support.348 Only Intel-based Apple's computers are supported (MacBook Pro,355 the laptop to act as a pinball machine-esque joystick.[all …]
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