Searched +full:bt1 +full:- +full:apb (Results 1 – 11 of 11) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Baikal-T1 APB-bus11 - Serge Semin <fancer.lancer@gmail.com>14 Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect15 which routes them to the AXI-APB bridge. This interface is a single master17 addressed APB slave devices. In case of any APB protocol collisions, slave19 reported to the APB terminator (APB Errors Handler Block).[all …]
1 # SPDX-License-Identifier: GPL-2.0-only3 ---4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Mark Brown <broonie@kernel.org>13 - $ref: "spi-controller.yaml#"14 - if:19 - mscc,ocelot-spi20 - mscc,jaguar2-spi25 - if:[all …]
1 // SPDX-License-Identifier: GPL-2.0-only8 * Baikal-T1 APB-bus driver38 * struct bt1_apb - Baikal-T1 APB EHB private data40 * @regs: APB EHB registers map.41 * @res: No-device error injection memory region.43 * @rate: APB-bus reference clock rate.44 * @pclk: APB-reference clock.45 * @prst: APB domain reset line.71 static inline unsigned long bt1_apb_n_to_timeout_us(struct bt1_apb *apb, u32 n) in bt1_apb_n_to_timeout_us() argument75 do_div(timeout, apb->rate); in bt1_apb_n_to_timeout_us()[all …]
1 # SPDX-License-Identifier: GPL-2.07 obj-$(CONFIG_ARM_CCI) += arm-cci.o8 obj-$(CONFIG_ARM_INTEGRATOR_LM) += arm-integrator-lm.o9 obj-$(CONFIG_HISILICON_LPC) += hisi_lpc.o10 obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o11 obj-$(CONFIG_MOXTET) += moxtet.o13 # DPAA2 fsl-mc bus14 obj-$(CONFIG_FSL_MC_BUS) += fsl-mc/16 obj-$(CONFIG_BT1_APB) += bt1-apb.o17 obj-$(CONFIG_BT1_AXI) += bt1-axi.o[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 // Baikal-T1 DW APB SPI and System Boot SPI driver24 #include <linux/spi/spi-mem.h>27 #include "spi-dw.h"52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()60 * mapped flash memory bounds and the operation is read-only. in dw_spi_bt1_dirmap_create()62 if (desc->info.offset + desc->info.length > dwsbt1->map_len || in dw_spi_bt1_dirmap_create()[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Baikal-T1 Clock Control Unit Dividers11 - Serge Semin <fancer.lancer@gmail.com>14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller18 IP-blocks or to groups of blocks (clock domains). The transformation is done19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The22 registers. Baikal-T1 CCU is logically divided into the next components:[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Baikal-T1 Clock Control Unit PLL11 - Serge Semin <fancer.lancer@gmail.com>14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller18 IP-blocks or to groups of blocks (clock domains). The transformation is done19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.23 2) PLLs clocks generators (PLLs) - described in this binding file.[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 * Baikal-T1 CCU PLL clocks driver12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt17 #include <linux/clk-provider.h>24 #include <dt-bindings/clock/bt1-ccu.h>26 #include "ccu-pll.h"56 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and57 * DDR controller AXI-bus clocks. If they are gated the system will be59 * of the corresponding subsystems. So until we aren't ready to re-initialize88 pll = data->plls[idx]; in ccu_pll_find_desc()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 * Baikal-T1 CCU Dividers clock driver12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt17 #include <linux/clk-provider.h>18 #include <linux/reset-controller.h>26 #include <dt-bindings/clock/bt1-ccu.h>27 #include <dt-bindings/reset/bt1-ccu.h>29 #include "ccu-div.h"138 * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks141 * the later is clocking the AXI-bus between DDR controller and the Main[all …]
1 # SPDX-License-Identifier: GPL-2.0-only3 ---4 $id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Synopsys DesignWare APB I2C Controller10 - Jarkko Nikula <jarkko.nikula@linux.intel.com>13 - $ref: /schemas/i2c/i2c-controller.yaml#14 - if:19 const: mscc,ocelot-i2c28 - description: Generic Synopsys DesignWare I2C controller[all …]
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