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/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/
H A Dhnd_debug.h39 #define HND_RAMSIZE_PTR_MAGIC 0x534d4152 /* RAMS */
75 uint32 magic; /* 'RAMS' */
/OK3568_Linux_fs/external/rkwifibt/drivers/infineon/include/
H A Dhnd_debug.h39 #define HND_RAMSIZE_PTR_MAGIC 0x534d4152 /* RAMS */
75 uint32 magic; /* 'RAMS' */
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/infineon/bcmdhd/include/
H A Dhnd_debug.h39 #define HND_RAMSIZE_PTR_MAGIC 0x534d4152 /* RAMS */
75 uint32 magic; /* 'RAMS' */
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/soc/ti/
H A Dti,pruss.yaml19 instruction RAMs, some internal peripheral modules to facilitate industrial
35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
92 The various Data RAMs within a single PRU-ICSS unit are represented as a
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/include/
H A Dhnd_debug.h38 #define HND_RAMSIZE_PTR_MAGIC 0x534d4152 /* RAMS */
75 uint32 magic; /* 'RAMS' */
/OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dmemory.json24 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
/OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/
H A Dexception.json8 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
/OK3568_Linux_fs/u-boot/include/
H A Dfsl_fman.h312 u32 fmrie; /* rams interrupt enable */
321 u32 fpmrcr; /* rams control and event */
369 /* FMFP_RCR - FMan Rams Control and Event */
/OK3568_Linux_fs/kernel/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h165 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
167 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
168 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/OK3568_Linux_fs/kernel/arch/arc/
H A DKconfig263 Single Cycle RAMS to store Fast Path Code
273 Single Cycle RAMS to store Fast Path Data
/OK3568_Linux_fs/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h171 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
173 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
174 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/OK3568_Linux_fs/kernel/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h172 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
174 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
175 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/OK3568_Linux_fs/kernel/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h185 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
187 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
188 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/OK3568_Linux_fs/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h197 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
199 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
200 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/OK3568_Linux_fs/kernel/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h218 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
220 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
221 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/OK3568_Linux_fs/kernel/drivers/misc/eeprom/
H A DKconfig5 tristate "I2C EEPROMs / RAMs / ROMs from most vendors"
/OK3568_Linux_fs/kernel/arch/powerpc/platforms/8xx/
H A DKconfig154 This microcode relocates SMC1 and SMC2 parameter RAMs at
/OK3568_Linux_fs/kernel/drivers/remoteproc/
H A Dti_k3_dsp_remoteproc.c224 * internal RAMs. The .prepare() ops is invoked by remoteproc core before any
350 * Custom function to translate a DSP device address (internal RAMs only) to a
351 * kernel virtual address. The DSPs can access their RAMs at either an internal
H A Dkeystone_remoteproc.c242 * Custom function to translate a DSP device address (internal RAMs only) to a
243 * kernel virtual address. The DSPs can access their RAMs at either an internal
/OK3568_Linux_fs/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h263 #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
265 #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
266 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/OK3568_Linux_fs/kernel/arch/xtensa/variants/csp/include/variant/
H A Dcore.h284 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
286 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
287 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/OK3568_Linux_fs/kernel/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h242 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
244 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
245 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/OK3568_Linux_fs/kernel/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h285 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
287 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
288 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/OK3568_Linux_fs/kernel/arch/xtensa/variants/de212/include/variant/
H A Dcore.h284 #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
286 #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
287 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dl2c2x0.yaml93 description: Cycles of latency for Dirty RAMs. This is a single cell.

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