1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyunconfig CPM1 3*4882a593Smuzhiyun bool 4*4882a593Smuzhiyun select CPM 5*4882a593Smuzhiyun 6*4882a593Smuzhiyunchoice 7*4882a593Smuzhiyun prompt "8xx Machine Type" 8*4882a593Smuzhiyun depends on PPC_8xx 9*4882a593Smuzhiyun default MPC885ADS 10*4882a593Smuzhiyun 11*4882a593Smuzhiyunconfig MPC8XXFADS 12*4882a593Smuzhiyun bool "FADS" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunconfig MPC86XADS 15*4882a593Smuzhiyun bool "MPC86XADS" 16*4882a593Smuzhiyun select CPM1 17*4882a593Smuzhiyun help 18*4882a593Smuzhiyun MPC86x Application Development System by Freescale Semiconductor. 19*4882a593Smuzhiyun The MPC86xADS is meant to serve as a platform for s/w and h/w 20*4882a593Smuzhiyun development around the MPC86X processor families. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunconfig MPC885ADS 23*4882a593Smuzhiyun bool "MPC885ADS" 24*4882a593Smuzhiyun select CPM1 25*4882a593Smuzhiyun select OF_DYNAMIC 26*4882a593Smuzhiyun help 27*4882a593Smuzhiyun Freescale Semiconductor MPC885 Application Development System (ADS). 28*4882a593Smuzhiyun Also known as DUET. 29*4882a593Smuzhiyun The MPC885ADS is meant to serve as a platform for s/w and h/w 30*4882a593Smuzhiyun development around the MPC885 processor family. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunconfig PPC_EP88XC 33*4882a593Smuzhiyun bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)" 34*4882a593Smuzhiyun select CPM1 35*4882a593Smuzhiyun help 36*4882a593Smuzhiyun This enables support for the Embedded Planet EP88xC board. 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun This board is also resold by Freescale as the QUICCStart 39*4882a593Smuzhiyun MPC885 Evaluation System and/or the CWH-PPC-885XN-VE. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunconfig PPC_ADDER875 42*4882a593Smuzhiyun bool "Analogue & Micro Adder 875" 43*4882a593Smuzhiyun select CPM1 44*4882a593Smuzhiyun help 45*4882a593Smuzhiyun This enables support for the Analogue & Micro Adder 875 46*4882a593Smuzhiyun board. 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunconfig TQM8XX 49*4882a593Smuzhiyun bool "TQM8XX" 50*4882a593Smuzhiyun select CPM1 51*4882a593Smuzhiyun help 52*4882a593Smuzhiyun support for the mpc8xx based boards from TQM. 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunendchoice 55*4882a593Smuzhiyun 56*4882a593Smuzhiyunmenu "Freescale Ethernet driver platform-specific options" 57*4882a593Smuzhiyun depends on (FS_ENET && MPC885ADS) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun config MPC8xx_SECOND_ETH 60*4882a593Smuzhiyun bool "Second Ethernet channel" 61*4882a593Smuzhiyun depends on MPC885ADS 62*4882a593Smuzhiyun default y 63*4882a593Smuzhiyun help 64*4882a593Smuzhiyun This enables support for second Ethernet on MPC885ADS and MPC86xADS boards. 65*4882a593Smuzhiyun The latter will use SCC1, for 885ADS you can select it below. 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun choice 68*4882a593Smuzhiyun prompt "Second Ethernet channel" 69*4882a593Smuzhiyun depends on MPC8xx_SECOND_ETH 70*4882a593Smuzhiyun default MPC8xx_SECOND_ETH_FEC2 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun config MPC8xx_SECOND_ETH_FEC2 73*4882a593Smuzhiyun bool "FEC2" 74*4882a593Smuzhiyun depends on MPC885ADS 75*4882a593Smuzhiyun help 76*4882a593Smuzhiyun Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2 77*4882a593Smuzhiyun (often 2-nd UART) will not work if this is enabled. 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun config MPC8xx_SECOND_ETH_SCC3 80*4882a593Smuzhiyun bool "SCC3" 81*4882a593Smuzhiyun depends on MPC885ADS 82*4882a593Smuzhiyun help 83*4882a593Smuzhiyun Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1 84*4882a593Smuzhiyun (often 1-nd UART) will not work if this is enabled. 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun endchoice 87*4882a593Smuzhiyun 88*4882a593Smuzhiyunendmenu 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun# 91*4882a593Smuzhiyun# MPC8xx Communication options 92*4882a593Smuzhiyun# 93*4882a593Smuzhiyun 94*4882a593Smuzhiyunmenu "MPC8xx CPM Options" 95*4882a593Smuzhiyun depends on PPC_8xx 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun# This doesn't really belong here, but it is convenient to ask 98*4882a593Smuzhiyun# 8xx specific questions. 99*4882a593Smuzhiyuncomment "Generic MPC8xx Options" 100*4882a593Smuzhiyun 101*4882a593Smuzhiyunconfig 8xx_GPIO 102*4882a593Smuzhiyun bool "GPIO API Support" 103*4882a593Smuzhiyun select GPIOLIB 104*4882a593Smuzhiyun help 105*4882a593Smuzhiyun Saying Y here will cause the ports on an MPC8xx processor to be used 106*4882a593Smuzhiyun with the GPIO API. If you say N here, the kernel needs less memory. 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun If in doubt, say Y here. 109*4882a593Smuzhiyun 110*4882a593Smuzhiyunconfig 8xx_CPU15 111*4882a593Smuzhiyun bool "CPU15 Silicon Errata" 112*4882a593Smuzhiyun depends on !HUGETLB_PAGE 113*4882a593Smuzhiyun default y 114*4882a593Smuzhiyun help 115*4882a593Smuzhiyun This enables a workaround for erratum CPU15 on MPC8xx chips. 116*4882a593Smuzhiyun This bug can cause incorrect code execution under certain 117*4882a593Smuzhiyun circumstances. This workaround adds some overhead (a TLB miss 118*4882a593Smuzhiyun every time execution crosses a page boundary), and you may wish 119*4882a593Smuzhiyun to disable it if you have worked around the bug in the compiler 120*4882a593Smuzhiyun (by not placing conditional branches or branches to LR or CTR 121*4882a593Smuzhiyun in the last word of a page, with a target of the last cache 122*4882a593Smuzhiyun line in the next page), or if you have used some other 123*4882a593Smuzhiyun workaround. 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun If in doubt, say Y here. 126*4882a593Smuzhiyun 127*4882a593Smuzhiyunchoice 128*4882a593Smuzhiyun prompt "Microcode patch selection" 129*4882a593Smuzhiyun default NO_UCODE_PATCH 130*4882a593Smuzhiyun help 131*4882a593Smuzhiyun Help not implemented yet, coming soon. 132*4882a593Smuzhiyun 133*4882a593Smuzhiyunconfig NO_UCODE_PATCH 134*4882a593Smuzhiyun bool "None" 135*4882a593Smuzhiyun 136*4882a593Smuzhiyunconfig USB_SOF_UCODE_PATCH 137*4882a593Smuzhiyun bool "USB SOF patch" 138*4882a593Smuzhiyun help 139*4882a593Smuzhiyun Help not implemented yet, coming soon. 140*4882a593Smuzhiyun 141*4882a593Smuzhiyunconfig I2C_SPI_UCODE_PATCH 142*4882a593Smuzhiyun bool "I2C/SPI relocation patch" 143*4882a593Smuzhiyun help 144*4882a593Smuzhiyun Help not implemented yet, coming soon. 145*4882a593Smuzhiyun 146*4882a593Smuzhiyunconfig I2C_SPI_SMC1_UCODE_PATCH 147*4882a593Smuzhiyun bool "I2C/SPI/SMC1 relocation patch" 148*4882a593Smuzhiyun help 149*4882a593Smuzhiyun Help not implemented yet, coming soon. 150*4882a593Smuzhiyun 151*4882a593Smuzhiyunconfig SMC_UCODE_PATCH 152*4882a593Smuzhiyun bool "SMC relocation patch" 153*4882a593Smuzhiyun help 154*4882a593Smuzhiyun This microcode relocates SMC1 and SMC2 parameter RAMs at 155*4882a593Smuzhiyun offset 0x1ec0 and 0x1fc0 to allow extended parameter RAM 156*4882a593Smuzhiyun for SCC3 and SCC4. 157*4882a593Smuzhiyun 158*4882a593Smuzhiyunendchoice 159*4882a593Smuzhiyun 160*4882a593Smuzhiyunconfig UCODE_PATCH 161*4882a593Smuzhiyun bool 162*4882a593Smuzhiyun default y 163*4882a593Smuzhiyun depends on !NO_UCODE_PATCH 164*4882a593Smuzhiyun 165*4882a593Smuzhiyunmenu "8xx advanced setup" 166*4882a593Smuzhiyun depends on PPC_8xx 167*4882a593Smuzhiyun 168*4882a593Smuzhiyunconfig PIN_TLB 169*4882a593Smuzhiyun bool "Pinned Kernel TLBs" 170*4882a593Smuzhiyun depends on ADVANCED_OPTIONS 171*4882a593Smuzhiyun help 172*4882a593Smuzhiyun On the 8xx, we have 32 instruction TLBs and 32 data TLBs. In each 173*4882a593Smuzhiyun table 4 TLBs can be pinned. 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun It reduces the amount of usable TLBs to 28 (ie by 12%). That's the 176*4882a593Smuzhiyun reason why we make it selectable. 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun This option does nothing, it just activate the selection of what 179*4882a593Smuzhiyun to pin. 180*4882a593Smuzhiyun 181*4882a593Smuzhiyunconfig PIN_TLB_DATA 182*4882a593Smuzhiyun bool "Pinned TLB for DATA" 183*4882a593Smuzhiyun depends on PIN_TLB 184*4882a593Smuzhiyun default y 185*4882a593Smuzhiyun help 186*4882a593Smuzhiyun This pins the first 32 Mbytes of memory with 8M pages. 187*4882a593Smuzhiyun 188*4882a593Smuzhiyunconfig PIN_TLB_IMMR 189*4882a593Smuzhiyun bool "Pinned TLB for IMMR" 190*4882a593Smuzhiyun depends on PIN_TLB 191*4882a593Smuzhiyun default y 192*4882a593Smuzhiyun help 193*4882a593Smuzhiyun This pins the IMMR area with a 512kbytes page. In case 194*4882a593Smuzhiyun CONFIG_PIN_TLB_DATA is also selected, it will reduce 195*4882a593Smuzhiyun CONFIG_PIN_TLB_DATA to 24 Mbytes. 196*4882a593Smuzhiyun 197*4882a593Smuzhiyunconfig PIN_TLB_TEXT 198*4882a593Smuzhiyun bool "Pinned TLB for TEXT" 199*4882a593Smuzhiyun depends on PIN_TLB 200*4882a593Smuzhiyun default y 201*4882a593Smuzhiyun help 202*4882a593Smuzhiyun This pins kernel text with 8M pages. 203*4882a593Smuzhiyun 204*4882a593Smuzhiyunendmenu 205*4882a593Smuzhiyun 206*4882a593Smuzhiyunendmenu 207