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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dti,j721e-cpb-ivi-audio.yaml22 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
26 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
36 PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
H A Dti,j721e-cpb-audio.yaml18 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
27 PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dqcom,mmcc-msm8960.h135 #define PLL15 126 macro
/OK3568_Linux_fs/kernel/sound/soc/ti/
H A Dj721e-evm.c205 clk_id == J721E_CLK_PARENT_48000 ? "PLL4" : "PLL15", in j721e_configure_refclk()
520 [J721E_CLK_PARENT_44100] = 1083801600, /* PLL15 */
529 [J721E_CLK_PARENT_44100] = 1083801600, /* PLL15 */
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dmmcc-msm8960.c67 "pll15",
124 static struct clk_pll pll15 = { variable
133 .name = "pll15",
2901 [PLL15] = &pll15.clkr,
3045 clk_pll_configure_sr(&pll15, regmap, &pll15_config, false); in mmcc_msm8960_probe()
/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/include/gaudi/
H A Dgaudi_async_ids_map_extended.h280 { .fc_id = 254, .cpu_id = 119, .valid = 1, .name = "PLL15" },