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/OK3568_Linux_fs/external/xserver/dix/
H A Deventconvert.c452 appendKeyInfo(DeviceChangedEvent *dce, xXIKeyInfo * info) in appendKeyInfo() argument
458 info->num_keycodes = dce->keys.max_keycode - dce->keys.min_keycode + 1; in appendKeyInfo()
460 info->sourceid = dce->sourceid; in appendKeyInfo()
464 *kc++ = i + dce->keys.min_keycode; in appendKeyInfo()
470 appendButtonInfo(DeviceChangedEvent *dce, xXIButtonInfo * info) in appendButtonInfo() argument
475 mask_len = bytes_to_int32(bits_to_bytes(dce->buttons.num_buttons)); in appendButtonInfo()
478 info->num_buttons = dce->buttons.num_buttons; in appendButtonInfo()
481 info->sourceid = dce->sourceid; in appendButtonInfo()
488 memcpy(bits, dce->buttons.names, dce->buttons.num_buttons * sizeof(Atom)); in appendButtonInfo()
494 appendValuatorInfo(DeviceChangedEvent *dce, xXIValuatorInfo * info, in appendValuatorInfo() argument
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H A Dgetevents.c258 DeviceChangedEvent *dce; in CreateClassesChangedEvent() local
261 dce = &event->changed_event; in CreateClassesChangedEvent()
262 memset(dce, 0, sizeof(DeviceChangedEvent)); in CreateClassesChangedEvent()
263 dce->deviceid = slave->id; in CreateClassesChangedEvent()
264 dce->masterid = master ? master->id : 0; in CreateClassesChangedEvent()
265 dce->header = ET_Internal; in CreateClassesChangedEvent()
266 dce->length = sizeof(DeviceChangedEvent); in CreateClassesChangedEvent()
267 dce->type = ET_DeviceChanged; in CreateClassesChangedEvent()
268 dce->time = ms; in CreateClassesChangedEvent()
269 dce->flags = flags; in CreateClassesChangedEvent()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_resource.c39 #include "dce/dce_mem_input.h"
40 #include "dce/dce_transform.h"
41 #include "dce/dce_link_encoder.h"
42 #include "dce/dce_stream_encoder.h"
43 #include "dce/dce_audio.h"
44 #include "dce/dce_opp.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_clock_source.h"
48 #include "dce/dce_hwseq.h"
50 #include "dce/dce_abm.h"
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_resource.c36 #include "dce/dce_audio.h"
40 #include "dce/dce_link_encoder.h"
41 #include "dce/dce_stream_encoder.h"
42 #include "dce/dce_mem_input.h"
44 #include "dce/dce_ipp.h"
45 #include "dce/dce_transform.h"
47 #include "dce/dce_opp.h"
49 #include "dce/dce_clock_source.h"
50 #include "dce/dce_hwseq.h"
52 #include "dce/dce_aux.h"
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H A Ddce110_opp_v.c29 #include "dce/dce_11_0_d.h"
30 #include "dce/dce_11_0_sh_mask.h"
32 #include "dce/dce_opp.h"
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.c29 #include "dce/dce_11_0_d.h"
30 #include "dce/dce_11_0_sh_mask.h"
183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
204 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
210 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
223 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce100/
H A Ddce100_resource.c39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_mem_input.h"
42 #include "dce/dce_ipp.h"
43 #include "dce/dce_transform.h"
44 #include "dce/dce_opp.h"
45 #include "dce/dce_clock_source.h"
46 #include "dce/dce_audio.h"
47 #include "dce/dce_hwseq.h"
49 #include "dce/dce_panel_cntl.h"
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/OK3568_Linux_fs/kernel/include/uapi/linux/hdlc/
H A Dioctl.h10 #define CLOCK_INT 2 /* Internal TX and RX clock - DCE */
65 unsigned short dce; /* 1 for DCE (network side) operation */ member
83 unsigned short dce; /* 1 for DCE (network side) operation */ member
/OK3568_Linux_fs/kernel/drivers/tty/serial/
H A Dicom.h70 u8 dce_resvd[20]; /* 1C8-1DB DCE Rsvd */
71 u8 dce_resvd21; /* 1DC DCE Rsvd (21st byte */
80 u8 dce_command; /* 1E7 dce command reg */
81 u8 dce_cmd_status; /* 1E8 dce command stat */
82 u8 x21_r1_ioff; /* 1E9 dce ready counter */
83 u8 x21_r0_ioff; /* 1EA dce not ready ctr */
84 u8 x21_ralt_ioff; /* 1EB dce CNR counter */
85 u8 x21_r1_ion; /* 1EC dce ready I on ctr */
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clk_mgr.c54 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
202 /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS in get_max_pixel_clock_for_all_paths()
227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
460 * the dce clock manager. This operation will overwrite the existing dprefclk
615 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
617 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
619 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
621 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
623 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
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H A DMakefile23 # Makefile for common 'dce' logic
29 DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \ macro
35 AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
H A Ddce_link_encoder.c40 #include "dce/dce_11_0_d.h"
41 #include "dce/dce_11_0_sh_mask.h"
42 #include "dce/dce_11_0_enum.h"
661 /*In DCE 11, we are able to pre-program a Force SR register in dce110_psr_program_dp_dphy_fast_training()
853 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dce110_link_encoder_construct()
858 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dce110_link_encoder_construct()
859 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dce110_link_encoder_construct()
860 * By this, adding DIGG should not hurt DCE 8.0. in dce110_link_encoder_construct()
861 * This will let DCE 8.1 share DCE 8.0 as much as possible in dce110_link_encoder_construct()
901 /* Override features with DCE-specific values */ in dce110_link_encoder_construct()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dio_link_encoder.c138 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn30_link_encoder_construct()
143 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn30_link_encoder_construct()
144 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn30_link_encoder_construct()
145 * By this, adding DIGG should not hurt DCE 8.0. in dcn30_link_encoder_construct()
146 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn30_link_encoder_construct()
188 /* Override features with DCE-specific values */ in dcn30_link_encoder_construct()
/OK3568_Linux_fs/u-boot/board/toradex/apalis_imx6/
H A DKconfig46 The UARTs must be used in DCE mode, RTS/CTS are swapped and
48 This option configures DCE mode unconditionally. Whithout this
49 option the config block stating V1.0 HW selects DCE mode,
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_resource.c28 #include "dce/dce_6_0_d.h"
29 #include "dce/dce_6_0_sh_mask.h"
42 #include "dce/dce_mem_input.h"
43 #include "dce/dce_link_encoder.h"
44 #include "dce/dce_stream_encoder.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_transform.h"
47 #include "dce/dce_opp.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce80/
H A Ddce80_resource.c28 #include "dce/dce_8_0_d.h"
29 #include "dce/dce_8_0_sh_mask.h"
42 #include "dce/dce_mem_input.h"
43 #include "dce/dce_link_encoder.h"
44 #include "dce/dce_stream_encoder.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_transform.h"
47 #include "dce/dce_opp.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
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H A Ddce80_hw_sequencer.c31 #include "dce/dce_hwseq.h"
36 #include "dce/dce_8_0_d.h"
37 #include "dce/dce_8_0_sh_mask.h"
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce120/
H A Ddce120_resource.c43 #include "dce/dce_opp.h"
44 #include "dce/dce_clock_source.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_mem_input.h"
47 #include "dce/dce_panel_cntl.h"
51 #include "dce/dce_transform.h"
53 #include "dce/dce_audio.h"
54 #include "dce/dce_link_encoder.h"
55 #include "dce/dce_stream_encoder.h"
56 #include "dce/dce_hwseq.h"
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_link_encoder.c378 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn21_link_encoder_construct()
383 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn21_link_encoder_construct()
384 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn21_link_encoder_construct()
385 * By this, adding DIGG should not hurt DCE 8.0. in dcn21_link_encoder_construct()
386 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn21_link_encoder_construct()
428 /* Override features with DCE-specific values */ in dcn21_link_encoder_construct()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
H A Ddce_clk_mgr.c43 #include "dce/dce_8_0_d.h"
44 #include "dce/dce_8_0_sh_mask.h"
70 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
183 /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS in dce_get_max_pixel_clock_for_all_paths()
208 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
218 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
401 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
/OK3568_Linux_fs/kernel/drivers/net/wan/
H A Dhdlc_fr.c11 DCE mode:
368 if (state(hdlc)->settings.dce) { in pvc_close()
483 int dce = state(hdlc)->settings.dce; in fr_lmi_send() local
489 if (dce && fullrep) { in fr_lmi_send()
511 data[i++] = dce ? LMI_STATUS : LMI_STATUS_ENQUIRY; in fr_lmi_send()
524 if (dce && fullrep) { in fr_lmi_send()
599 if (!state(hdlc)->settings.dce) in fr_set_link_state()
615 if (state(hdlc)->settings.dce) { in fr_timer()
640 if (state(hdlc)->settings.dce) in fr_timer()
665 int dce = state(hdlc)->settings.dce; in fr_lmi_recv() local
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/
H A Ddce60_clk_mgr.c43 #include "dce/dce_6_0_d.h"
44 #include "dce/dce_6_0_sh_mask.h"
74 /* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
126 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce60_update_clocks()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_link_encoder.c436 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn20_link_encoder_construct()
441 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn20_link_encoder_construct()
442 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn20_link_encoder_construct()
443 * By this, adding DIGG should not hurt DCE 8.0. in dcn20_link_encoder_construct()
444 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn20_link_encoder_construct()
486 /* Override features with DCE-specific values */ in dcn20_link_encoder_construct()
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/arm-none-linux-gnueabihf/libc/usr/include/linux/hdlc/
H A Dioctl.h10 #define CLOCK_INT 2 /* Internal TX and RX clock - DCE */
65 unsigned short dce; /* 1 for DCE (network side) operation */ member
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/aarch64-none-linux-gnu/libc/usr/include/linux/hdlc/
H A Dioctl.h10 #define CLOCK_INT 2 /* Internal TX and RX clock - DCE */
65 unsigned short dce; /* 1 for DCE (network side) operation */ member

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