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/OK3568_Linux_fs/u-boot/arch/arm/mach-keystone/
H A Dclock.c4 * (C) Copyright 2012-2014
7 * SPDX-License-Identifier: GPL-2.0+
47 if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK)) in wait_for_completion()
54 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK | in bypass_main_pll()
63 u32 pllm, plld, bwadj; in configure_mult_div() local
65 pllm = data->pll_m - 1; in configure_mult_div()
66 plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK; in configure_mult_div()
69 if (data->pll == MAIN_PLL) in configure_mult_div()
70 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); in configure_mult_div()
72 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, in configure_mult_div()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
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/OK3568_Linux_fs/kernel/drivers/soc/kendryte/
H A Dk210-sysctl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/clk-provider.h>
23 /* clkr: 4bits, clkf1: 6bits, clkod: 4bits, bwadj: 4bits */
143 clksel0 = readl(s->regs + K210_SYSCTL_CLKSEL0); in k210_sysctl_clk_recalc_rate()
151 pll0 = readl(s->regs + K210_SYSCTL_PLL0); in k210_sysctl_clk_recalc_rate()
166 .name = "k210-sysctl-pll1",
177 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL); in k210_sysctl_probe()
179 return -ENOMEM; in k210_sysctl_probe()
181 s->regs = devm_ioremap_resource(&pdev->dev, in k210_sysctl_probe()
183 if (IS_ERR(s->regs)) in k210_sysctl_probe()
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/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c3 * Author: Andy Yan <andy.yan@rock-chips.com>
5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
21 #include <dt-bindings/clock/rk3368-cru.h>
154 return -EINVAL; in pll_para_config()
165 div->nr = best_div->nr; in pll_para_config()
166 div->nf = best_div->nf; in pll_para_config()
167 div->no = best_div->no; in pll_para_config()
168 div->nb = best_div->nb; in pll_para_config()
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/OK3568_Linux_fs/kernel/drivers/crypto/cavium/nitrox/
H A Dnitrox_csr.h1 /* SPDX-License-Identifier: GPL-2.0 */
151 /* Mailbox PF->VF PF Accessible Data registers */
206 * struct ucd_core_eid_ucode_block_num - Core Eid to Ucode Blk Mapping Registers
226 * struct aqm_grp_execmsk_lo - Available AE engines for the group
243 * struct aqm_grp_execmsk_hi - Available AE engines for the group
260 * struct aqmq_drbl - AQM Queue Doorbell Counter Registers
277 * struct aqmq_qsz - AQM Queue Host Queue Size Registers
295 * struct aqmq_cmp_thr - AQM Queue Commands Completed Threshold Registers
313 * struct aqmq_cmp_cnt - AQM Queue Commands Completed Count Registers
337 * struct aqmq_en - AQM Queue Enable Registers
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