Searched +full:0 +full:x2040000 (Results 1 – 7 of 7) sorted by relevance
74 reg = <0x1f059000 0x1000>,75 <0x1d000000 0x2040000>;
11 reg = <0x00 0x70000000 0x00 0x100000>;14 ranges = <0x00 0x00 0x70000000 0x100000>;16 atf-sram@0 {17 reg = <0x00 0x20000>;23 reg = <0x00 0x00100000 0x00 0x1c000>;26 ranges = <0x00 0x00 0x00100000 0x1c000>;31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */32 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */38 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */49 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */[all …]
13 #clock-cells = <0>;15 clock-frequency = <0>;19 #clock-cells = <0>;21 clock-frequency = <0>;28 reg = <0x0 0x70000000 0x0 0x800000>;31 ranges = <0x0 0x0 0x70000000 0x800000>;33 atf-sram@0 {34 reg = <0x0 0x20000>;40 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */43 ranges = <0x0 0x0 0x00100000 0x1c000>;[all …]
26 #size-cells = <0>;28 cpu0: cpu@0 {31 reg = <0x0>;33 clocks = <&clockgen 1 0>;42 reg = <0x1>;44 clocks = <&clockgen 1 0>;65 arm,psci-suspend-param = <0x0>;74 #clock-cells = <0>;81 #clock-cells = <0>;88 reg = <0x0 0xf1f0000 0x0 0xffff>;[all …]
11 /memreserve/ 0x80000000 0x00010000;25 #size-cells = <0>;28 cpu0: cpu@0 {32 reg = <0x0>;33 clocks = <&clockgen 1 0>;34 d-cache-size = <0x8000>;37 i-cache-size = <0xC000>;49 reg = <0x1>;50 clocks = <&clockgen 1 0>;51 d-cache-size = <0x8000>;[all …]
55 #define RK_PCIE_DBG 057 #define PCIE_DMA_OFFSET 0x38000059 #define PCIE_DMA_CTRL_OFF 0x860 #define PCIE_DMA_WR_ENB 0xc61 #define PCIE_DMA_WR_CTRL_LO 0x20062 #define PCIE_DMA_WR_CTRL_HI 0x20463 #define PCIE_DMA_WR_XFERSIZE 0x20864 #define PCIE_DMA_WR_SAR_PTR_LO 0x20c65 #define PCIE_DMA_WR_SAR_PTR_HI 0x21066 #define PCIE_DMA_WR_DAR_PTR_LO 0x214[all …]
37 * Generated by: IDF:x 1.3.056 #define ATV_COMM_EXEC__A 0xC0000058 #define ATV_COMM_EXEC__M 0x359 #define ATV_COMM_EXEC__PRE 0x060 #define ATV_COMM_EXEC_STOP 0x061 #define ATV_COMM_EXEC_ACTIVE 0x162 #define ATV_COMM_EXEC_HOLD 0x264 #define ATV_COMM_STATE__A 0xC0000166 #define ATV_COMM_STATE__M 0xFFFF67 #define ATV_COMM_STATE__PRE 0x0[all …]