Searched +full:0 +full:x01c0a000 (Results 1 – 6 of 6) sorted by relevance
47 reg = <0x01c0a000 0x1000>;49 resets = <&tcon_ch0_clk 0>;
64 reg = <0x01c0a000 0x1000>;66 resets = <&tcon_ch0_clk 0>;71 #size-cells = <0>;73 tve0_in_tcon0: endpoint@0 {74 reg = <0>;
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;78 #clock-cells = <0>;80 clock-frequency = <0>;84 #clock-cells = <0>;86 reg = <0x01c20050 0x4>;93 #clock-cells = <0>;100 osc32k: clk@0 {101 #clock-cells = <0>;[all …]
12 #define SUNXI_SRAM_A1_BASE 0x0000000015 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */16 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */17 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */18 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */19 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */21 #define SUNXI_DE2_BASE 0x0100000024 #define SUNXI_CPUCFG_BASE 0x0170000027 #define SUNXI_SRAMC_BASE 0x01c0000028 #define SUNXI_DRAMC_BASE 0x01c01000[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;97 #clock-cells = <0>;104 #clock-cells = <0>;119 size = <0x6000000>;120 alloc-ranges = <0x40000000 0x10000000>;135 reg = <0x01c00000 0x30>;140 sram_a: sram@0 {142 reg = <0x00000000 0xc000>;[all …]
73 reg = <0 0x80000000 0 0>;82 reg = <0 0x85700000 0 0x600000>;87 reg = <0 0x85e00000 0 0x100000>;92 reg = <0 0x85fc0000 0 0x20000>;98 reg = <0x0 0x85fe0000 0 0x20000>;103 reg = <0x0 0x86000000 0 0x200000>;108 reg = <0 0x86200000 0 0x2d00000>;114 reg = <0 0x88f00000 0 0x200000>;122 reg = <0 0x8ab00000 0 0x1400000>;127 reg = <0 0x8bf00000 0 0x500000>;[all …]