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Searched defs:val (Results 1 – 25 of 156) sorted by relevance

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/optee_os/core/drivers/crypto/caam/hal/common/registers/
H A Drng_regs.h27 #define GET_TRNG_SDCTL_ENT_DLY(val) (((val) & BM_TRNG_SDCTL_ENT_DLY) >> 16) argument
28 #define TRNG_SDCTL_ENT_DLY(val) SHIFT_U32(((val) & 0xFFFF), 16) argument
29 #define TRNG_SDCTL_SAMP_SIZE(val) ((val) & 0xFFFF) argument
46 #define TRNG_RTSCMISC_RTY_CNT(val) SHIFT_U32(((val) & (0xF)), 16) argument
48 #define TRNG_RTSCMISC_LRUN_MAX(val) SHIFT_U32(((val) & (0xFF)), 0) argument
53 #define TRNG_RTPKRRNG_PKR_RNG(val) SHIFT_U32(((val) & (0xFFFF)), 0) argument
58 #define TRNG_RTPKRMAX_PKR_MAX(val) SHIFT_U32(((val) & (0xFFFFFF)), 0) argument
63 #define TRNG_RTSCML_MONO_RNG(val) SHIFT_U32(((val) & (0xFFFF)), 16) argument
65 #define TRNG_RTSCML_MONO_MAX(val) SHIFT_U32(((val) & (0xFFFF)), 0) argument
70 #define TRNG_RTSCR1L_RUN1_RNG(val) SHIFT_U32(((val) & (0x7FFF)), 16) argument
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H A Dversion_regs.h15 #define GET_CTPR_MS_RNG_I(val) (((val) & BM_CTPR_MS_RNG_I) >> 8) argument
19 #define GET_CTPR_LS_SPLIT_KEY(val) (((val) & BM_CTPR_LS_SPLIT_KEY) >> 14) argument
24 #define GET_SMVID_MS_MAX_NPAG(val) (((val) & BM_SMVID_MS_MAX_NPAG) >> 16) argument
26 #define GET_SMVID_MS_NPRT(val) (((val) & BM_SMVID_MS_NPRT) >> 12) argument
30 #define GET_SMVID_LS_PSIZ(val) (((val) & BM_SMVID_LS_PSIZ) >> 16) argument
35 #define GET_CCBVID_CAAM_ERA(val) (((val) & BM_CCBVID_CAAM_ERA) >> 24) argument
40 #define GET_CHAVID_LS_RNGVID(val) (((val) & BM_CHAVID_LS_RNGVID) >> 16) argument
48 #define GET_CHANUM_MS_JRNUM(val) (((val) & BM_CHANUM_MS_JRNUM) >> 28) argument
52 #define GET_CHANUM_LS_PKNUM(val) (((val) & BM_CHANUM_LS_PKNUM) >> 28) argument
54 #define GET_CHANUM_LS_MDNUM(val) (((val) & BM_CHANUM_LS_MDNUM) >> 12) argument
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H A Dsm_regs.h34 #define SM_SMCSR_CERR(val) (((val) >> 14) & 0x3) argument
37 #define SM_SMCSR_AERR(val) (((val) >> 12) & 0x3) argument
39 #define SM_SMCSR_PO(val) (((val) >> 6) & 0x3) argument
44 #define SM_SMCSR_PRTN(val) ((val) & 0x3) argument
49 #define SM_SMPO_OWNER(val, prtn) (((val) >> SM_SMPO_PART(prtn)) & 0x3) argument
/optee_os/core/drivers/crypto/caam/hal/common/
H A Dhal_ctrl.c22 uint32_t val = io_caam_read32(baseaddr + CCBVID); in caam_hal_ctrl_era() local
29 uint32_t val = 0; in caam_hal_ctrl_jrnum() local
45 uint32_t val = 0; in caam_hal_ctrl_hash_limit() local
79 uint32_t val = io_caam_read32(baseaddr + CTPR_LS); in caam_hal_ctrl_splitkey_support() local
86 uint32_t val = 0; in caam_hal_ctrl_pknum() local
104 uint32_t val = 0; in caam_hal_ctrl_inc_priblob() local
173 uint32_t val = 0; in caam_hal_ctrl_read_mpmr() local
203 uint32_t val = 0; in caam_hal_ctrl_fill_mpmr() local
H A Dhal_jr.c158 uint32_t val = 0; in caam_hal_jr_check_ack_itr() local
174 uint32_t val = 0; in caam_hal_jr_halt() local
204 uint32_t val = 0; in caam_hal_jr_flush() local
/optee_os/core/drivers/crypto/caam/hal/imx_6_7/registers/
H A Dctrl_regs.h15 #define MCFGR_AXIPIPE(val) SHIFT_U32(val, 4) argument
30 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0x7, 0) argument
33 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0x7, 16) argument
35 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0x7, 0) argument
38 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0xF, 0) argument
41 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0xF, 16) argument
43 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0xF, 0) argument
/optee_os/core/include/
H A Dio.h25 static inline void io_write8(vaddr_t addr, uint8_t val) in io_write8()
30 static inline void io_write16(vaddr_t addr, uint16_t val) in io_write16()
35 static inline void io_write32(vaddr_t addr, uint32_t val) in io_write32()
40 static inline void io_write64(vaddr_t addr, uint64_t val) in io_write64()
65 static inline void io_mask8(vaddr_t addr, uint8_t val, uint8_t mask) in io_mask8()
70 static inline void io_mask16(vaddr_t addr, uint16_t val, uint16_t mask) in io_mask16()
75 static inline void io_mask32(vaddr_t addr, uint32_t val, uint32_t mask) in io_mask32()
85 static inline void put_be64(void *p, uint64_t val) in put_be64()
95 static inline void put_be32(void *p, uint32_t val) in put_be32()
105 static inline void put_be16(void *p, uint16_t val) in put_be16()
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/optee_os/core/include/dt-bindings/gpio/
H A Datmel,piobu.h11 #define PIOBU_PIN_AFV(val) (((val) & PIOBU_PIN_AFV_MASK) >> \ argument
16 #define PIOBU_PIN_RFV(val) (((val) & PIOBU_PIN_RFV_MASK) >> \ argument
21 #define PIOBU_PIN_PULL_MODE(val) (((val) & PIOBU_PIN_PULL_MODE_MASK) >> \ argument
29 #define PIOBU_PIN_DEF_LEVEL(val) (((val) & PIOBU_PIN_DEF_LEVEL_MASK) >> \ argument
36 #define PIOBU_PIN_WAKEUP(val) (((val) & PIOBU_PIN_WAKEUP_MASK) >> \ argument
/optee_os/core/drivers/crypto/caam/hal/ls/registers/
H A Dctrl_regs.h15 #define MCFGR_AXIPIPE(val) SHIFT_U32(val, 4) argument
30 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0x7, 0) argument
33 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0x7, 16) argument
35 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0x7, 0) argument
/optee_os/lib/libutils/ext/include/
H A Datomic.h46 static inline void atomic_store_int(int *p, int val) in atomic_store_int()
51 static inline void atomic_store_short(short int *p, short int val) in atomic_store_short()
56 static inline void atomic_store_uint(unsigned int *p, unsigned int val) in atomic_store_uint()
61 static inline void atomic_store_u32(uint32_t *p, uint32_t val) in atomic_store_u32()
/optee_os/core/include/kernel/
H A Drefcount.h51 unsigned int val; member
59 static inline void refcount_set(struct refcount *r, unsigned int val) in refcount_set()
/optee_os/core/arch/arm/plat-marvell/armada3700/
H A Dhal_sec_perf.c70 #define TZ_SET_PERM(data, val) \ argument
77 #define TZ_SET_RZ_EN(data, val) \ argument
85 #define TZ_SET_AREA_LEN_CODE(data, val) \ argument
94 #define TZ_SET_START_ADDR_L(data, val) \ argument
100 #define TZ_GET_UR_PERM(data, val) ((ret) = (((data) & (0x3 << 4)) >> 4)) argument
101 #define TZ_SET_UR_PERM(data, val) \ argument
107 #define TZ_GET_UR_RZ_EN(data, val) \ argument
110 #define TZ_SET_UR_RZ_EN(data, val) \ argument
/optee_os/core/lib/libfdt/
H A Dfdt_addresses.c17 uint32_t val; in fdt_cells() local
36 int val; in fdt_address_cells() local
48 int val; in fdt_size_cells() local
/optee_os/core/arch/arm/plat-marvell/armada7k8k/
H A Dhal_sec_perf.c69 #define TZ_SET_PERM(data, val) \ argument
76 #define TZ_SET_RZ_EN(data, val) \ argument
84 #define TZ_SET_AREA_LEN_CODE(data, val) \ argument
93 #define TZ_SET_START_ADDR_L(data, val) \ argument
99 #define TZ_GET_UR_PERM(data, val) ((ret) = (((data) & (0x3 << 4)) >> 4)) argument
100 #define TZ_SET_UR_PERM(data, val) \ argument
106 #define TZ_GET_UR_RZ_EN(data, val) \ argument
109 #define TZ_SET_UR_RZ_EN(data, val) \ argument
/optee_os/core/lib/libfdt/include/
H A Dlibfdt.h1285 const char *name, uint32_t val) in fdt_setprop_inplace_u32()
1320 const char *name, uint64_t val) in fdt_setprop_inplace_u64()
1332 const char *name, uint32_t val) in fdt_setprop_inplace_cell()
1435 static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) in fdt_property_u32()
1440 static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) in fdt_property_u64()
1447 static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) in fdt_property_cell()
1646 uint32_t val) in fdt_setprop_u32()
1681 uint64_t val) in fdt_setprop_u64()
1693 uint32_t val) in fdt_setprop_cell()
1818 const char *name, uint32_t val) in fdt_appendprop_u32()
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/optee_os/core/arch/arm/plat-zynq7k/
H A Dmain.c133 uint32_t val; in arm_cl2_enable() local
161 static uint32_t write_slcr(uint32_t addr, uint32_t val) in write_slcr()
182 static uint32_t read_slcr(uint32_t addr, uint32_t *val) in read_slcr()
/optee_os/core/drivers/
H A Dtzc400.c92 static void tzc_write_gate_keeper(vaddr_t base, uint32_t val) in tzc_write_gate_keeper()
108 uint32_t val) in tzc_write_region_base_low()
119 uint32_t val) in tzc_write_region_base_high()
130 uint32_t val) in tzc_write_region_top_low()
141 uint32_t val) in tzc_write_region_top_high()
152 uint32_t val) in tzc_write_region_attributes()
163 uint32_t val) in tzc_write_region_id_access()
191 static void tzc_set_gate_keeper(vaddr_t base, uint8_t filter, uint32_t val) in tzc_set_gate_keeper()
H A Dhisi_trng.c26 static TEE_Result trng_read(uint32_t *val) in trng_read()
46 uint32_t val = 0; in hw_get_random_bytes() local
H A Dtzc380.c71 uint32_t val) in tzc_write_region_base_low()
77 uint32_t val) in tzc_write_region_base_high()
88 uint32_t val) in tzc_write_region_attributes()
128 uint32_t val; in tzc_region_enable() local
300 uint32_t val = 0; in tzc_regions_lockdown() local
H A Dimsic.c61 static void imsic_csr_write(unsigned long reg, unsigned long val) in imsic_csr_write()
73 static void imsic_csr_set(unsigned long reg, unsigned long val) in imsic_csr_set()
79 static void imsic_csr_clear(unsigned long reg, unsigned long val) in imsic_csr_clear()
107 uint32_t val = swap_csr(CSR_XTOPEI, 0); in imsic_claim_interrupt() local
113 bool pend, bool val) in imsic_local_eix_update()
252 const fdt32_t *val = NULL; in imisc_parse_fdt_node() local
H A Dopenedges_omc.c79 static void omc_write32(uint8_t filter, uint32_t offs, uint32_t val) in omc_write32()
93 static void omc_write64(uint8_t filter, uint32_t offs, uint64_t val) in omc_write64()
107 static void omc_write_region_base(uint8_t filter, uint32_t region, uint64_t val) in omc_write_region_base()
112 static void omc_write_region_top(uint8_t filter, uint32_t region, uint64_t val) in omc_write_region_top()
118 uint32_t val) in omc_write_region_attributes()
125 uint32_t val) in omc_write_region_id_access()
/optee_os/core/pta/imx/
H A Docotp.c15 uint8_t val[IMX_UID_SIZE] = { }; in chip_uid() local
40 uint32_t val = 0; in read_fuse() local
/optee_os/core/drivers/crypto/caam/hal/imx_8q/registers/
H A Dctrl_regs.h19 #define JRxDID_MS_PRIM_ICID(val) SHIFT_U32((val) & (0x3FF), 19) argument
24 #define JRxDID_MS_PRIM_DID(val) SHIFT_U32((val) & (0xF), 0) argument
/optee_os/core/arch/arm/include/
H A Darm32_macros.S11 .macro mov_imm reg, val
/optee_os/core/drivers/crypto/caam/include/
H A Dcaam_io.h18 #define io_caam_write32(a, val) io_write32(a, TEE_U32_TO_BIG_ENDIAN(val)) argument
26 #define io_caam_write32(a, val) io_write32(a, val) argument

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