1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (C) 2025, STMicroelectronics
4 */
5
6 #include <assert.h>
7 #include <config.h>
8 #include <drivers/clk_dt.h>
9 #include <drivers/stm32_rif.h>
10 #include <drivers/stm32_shared_io.h>
11 #include <drivers/stm32mp21_rcc.h>
12 #include <drivers/stm32mp_dt_bindings.h>
13 #include <initcall.h>
14 #include <io.h>
15 #include <kernel/dt.h>
16 #include <kernel/panic.h>
17 #include <kernel/pm.h>
18 #include <libfdt.h>
19 #include <stdbool.h>
20 #include <stdio.h>
21 #include <stm32_sysconf.h>
22 #include <stm32_util.h>
23 #include <trace.h>
24 #include <util.h>
25
26 #include "clk-stm32-core.h"
27
28 #define MAX_OPP CFG_STM32MP_OPP_COUNT
29
30 #define RCC_SECCFGR(x) (U(0x0) + U(0x4) * (x))
31 #define RCC_PRIVCFGR(x) (U(0x10) + U(0x4) * (x))
32 #define RCC_RCFGLOCKR(x) (U(0x20) + U(0x4) * (x))
33 #define RCC_CIDCFGR(x) (U(0x030) + U(0x08) * (x))
34 #define RCC_SEMCR(x) (U(0x034) + U(0x08) * (x))
35
36 #define TIMEOUT_US_100MS U(100000)
37 #define TIMEOUT_US_200MS U(200000)
38 #define TIMEOUT_US_1S U(1000000)
39
40 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS
41 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS
42 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS
43 #define OSCRDY_TIMEOUT TIMEOUT_US_1S
44
45 /* PLL minimal frequencies for clock sources */
46 #define PLL_REFCLK_MIN UL(5000000)
47 #define PLL_FRAC_REFCLK_MIN UL(10000000)
48
49 /* Parameters from XBAR_CFG in st,cksrc field */
50 #define XBAR_CKSRC_CHANNEL GENMASK_32(5, 0)
51 #define XBAR_CKSRC_SRC GENMASK_32(9, 6)
52 #define XBAR_CKSRC_SRC_OFFSET U(6)
53 #define XBAR_CKSRC_PREDIV GENMASK_32(19, 10)
54 #define XBAR_CKSRC_PREDIV_OFFSET U(10)
55 #define XBAR_CKSRC_FINDIV GENMASK_32(25, 20)
56 #define XBAR_CKSRC_FINDIV_OFFSET U(20)
57
58 #define XBAR_CHANNEL_NB U(64)
59 #define XBAR_ROOT_CHANNEL_NB U(6)
60
61 #define FLEX_STGEN U(33)
62
63 #define RCC_0_MHZ UL(0)
64 #define RCC_4_MHZ UL(4000000)
65 #define RCC_16_MHZ UL(16000000)
66
67 /*
68 * CIDCFGR register bitfields
69 */
70 #define RCC_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16)
71 #define RCC_CIDCFGR_SCID_MASK GENMASK_32(6, 4)
72 #define RCC_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | \
73 _CIDCFGR_SEMEN | \
74 RCC_CIDCFGR_SCID_MASK |\
75 RCC_CIDCFGR_SEMWL_MASK)
76
77 /*
78 * SECCFGR register bitfields
79 */
80 #define RCC_SECCFGR_EN BIT(0)
81
82 /*
83 * SEMCR register bitfields
84 */
85 #define RCC_SEMCR_SCID_MASK GENMASK_32(6, 4)
86 #define RCC_SEMCR_SCID_SHIFT U(4)
87
88 /*
89 * RIF miscellaneous
90 */
91
92 #define RCC_NB_RIF_RES U(114)
93 #define RCC_NB_CONFS DIV_ROUND_UP(RCC_NB_RIF_RES, 32)
94
95 /* Register: RCC_RxCIDCFGR */
96 #define RCC_CIDCFGR_CFEN BIT(0)
97 #define RCC_CIDCFGR_SEM_EN BIT(1)
98 #define RCC_CIDCFGR_SCID_SHIFT 4
99 #define RCC_SEMWL_SHIFT 16
100
101 /* Compartiment IDs */
102 #define RIF_CID0 0x0
103 #define RIF_CID1 0x1
104 #define RIF_CID2 0x2
105
106 /* RCC RIF resource IDs */
107 #define RCC_RIF_PLL4_TO_8 64
108 #define RCC_RIF_FCAL 65
109 #define RCC_RIF_SYSTEM_RESET 66
110 #define RCC_RIF_RCC_CPU_BOOT 67
111 #define RCC_RIF_RESET_DURATION 68
112 #define RCC_RIF_OSCILLATORS 69
113 #define RCC_RIF_DEBUG_TRACE 73
114 #define RCC_RIF_SYSRAM 74
115 #define RCC_RIF_RETRAM 76
116 #define RCC_RIF_BKPSRAM 77
117 #define RCC_RIF_SRAM1 78
118 #define RCC_RIF_HPDMA1 83
119 #define RCC_RIF_HPDMA2 84
120 #define RCC_RIF_HPDMA3 85
121 #define RCC_RIF_IPCC1 87
122 #define RCC_RIF_GPIOA 90
123 #define RCC_RIF_GPIOB 91
124 #define RCC_RIF_GPIOC 92
125 #define RCC_RIF_GPIOD 93
126 #define RCC_RIF_GPIOE 94
127 #define RCC_RIF_GPIOF 95
128 #define RCC_RIF_GPIOG 96
129 #define RCC_RIF_GPIOH 97
130 #define RCC_RIF_GPIOI 98
131 #define RCC_RIF_GPIOZ 101
132 #define RCC_RIF_RTC_TAMP 102
133 #define RCC_RIF_BSEC 103
134 #define RCC_RIF_DDR_PLL2 104
135 #define RCC_RIF_SYSCPU1 106
136 #define RCC_RIF_MCO1 108
137 #define RCC_RIF_MCO2 109
138 #define RCC_RIF_OSPI1 110
139 #define RCC_RIF_FMC 112
140 #define RCC_RIF_HSIFMON 113
141
142 enum pll_cfg {
143 FBDIV,
144 REFDIV,
145 POSTDIV1,
146 POSTDIV2,
147 PLLCFG_NB
148 };
149
150 enum pll_csg {
151 DIVVAL,
152 SPREAD,
153 DOWNSPREAD,
154 PLLCSG_NB
155 };
156
157 struct stm32_pll_dt_cfg {
158 uint32_t cfg[PLLCFG_NB];
159 uint32_t csg[PLLCSG_NB];
160 uint32_t frac;
161 uint32_t src;
162 bool enabled;
163 bool csg_enabled;
164 };
165
166 struct stm32_osci_dt_cfg {
167 unsigned long freq;
168 uint32_t drive;
169 bool bypass;
170 bool digbyp;
171 bool css;
172 };
173
174 struct stm32_clk_opp_cfg {
175 uint32_t frq;
176 struct stm32_pll_dt_cfg pll_cfg;
177 };
178
179 struct stm32_clk_opp_dt_cfg {
180 struct stm32_clk_opp_cfg cpu1_opp[MAX_OPP];
181 };
182
183 struct stm32_clk_platdata {
184 uintptr_t rcc_base;
185 uint32_t nosci;
186 struct stm32_osci_dt_cfg *osci;
187 uint32_t npll;
188 struct stm32_pll_dt_cfg *pll;
189 struct stm32_clk_opp_dt_cfg *opp;
190 struct rif_conf_data conf_data;
191 unsigned int nb_res;
192 uint32_t nbusclk;
193 uint32_t *busclk;
194 uint32_t nkernelclk;
195 uint32_t *kernelclk;
196 uint32_t nflexgen;
197 uint32_t *flexgen;
198 uint32_t c1msrd;
199 bool safe_rst;
200 };
201
202 /*
203 * GATE CONFIG
204 */
205
206 /* WARNING GATE_XXX_RDY MUST FOLLOW GATE_XXX */
207
208 enum enum_gate_cfg {
209 GATE_HSI,
210 GATE_HSI_RDY,
211 GATE_HSI_KER,
212 GATE_HSE,
213 GATE_HSE_RDY,
214 GATE_HSE_KER,
215 GATE_LSE,
216 GATE_LSE_RDY,
217 GATE_LSI,
218 GATE_LSI_RDY,
219 GATE_MSI,
220 GATE_MSI_RDY,
221 GATE_MSI_KER,
222 GATE_PLL1,
223 GATE_PLL1_RDY,
224 GATE_PLL2,
225 GATE_PLL2_RDY,
226 GATE_PLL4,
227 GATE_PLL4_RDY,
228 GATE_PLL5,
229 GATE_PLL5_RDY,
230 GATE_PLL6,
231 GATE_PLL6_RDY,
232 GATE_PLL7,
233 GATE_PLL7_RDY,
234 GATE_PLL8,
235 GATE_PLL8_RDY,
236 GATE_PLL4_CKREFST,
237 GATE_PLL5_CKREFST,
238 GATE_PLL6_CKREFST,
239 GATE_PLL7_CKREFST,
240 GATE_PLL8_CKREFST,
241 GATE_HSEDIV2,
242 GATE_APB1DIV_RDY,
243 GATE_APB2DIV_RDY,
244 GATE_APB3DIV_RDY,
245 GATE_APB4DIV_RDY,
246 GATE_APB5DIV_RDY,
247 GATE_APBDBGDIV_RDY,
248 GATE_TIMG1PRE_RDY,
249 GATE_TIMG2PRE_RDY,
250 GATE_LSMCUDIV_RDY,
251 GATE_RTCCK,
252 GATE_MCO1,
253 GATE_MCO2,
254 GATE_DDRCP,
255 GATE_DDRCAPB,
256 GATE_DDRPHYCAPB,
257 GATE_DDRPHYC,
258 GATE_DDRCFG,
259 GATE_SYSRAM,
260 GATE_SRAM1,
261 GATE_RETRAM,
262 GATE_BKPSRAM,
263 GATE_OSPI1,
264 GATE_FMC,
265 GATE_DBG,
266 GATE_DBGMCU,
267 GATE_TRACE,
268 GATE_STM,
269 GATE_ETR,
270 GATE_GPIOA,
271 GATE_GPIOB,
272 GATE_GPIOC,
273 GATE_GPIOD,
274 GATE_GPIOE,
275 GATE_GPIOF,
276 GATE_GPIOG,
277 GATE_GPIOH,
278 GATE_GPIOI,
279 GATE_GPIOZ,
280 GATE_HPDMA1,
281 GATE_HPDMA2,
282 GATE_HPDMA3,
283 GATE_IPCC1,
284 GATE_RTC,
285 GATE_SYSCPU1,
286 GATE_BSEC,
287 GATE_HSIMON,
288 GATE_TIM1,
289 GATE_TIM2,
290 GATE_TIM3,
291 GATE_TIM4,
292 GATE_TIM5,
293 GATE_TIM6,
294 GATE_TIM7,
295 GATE_TIM8,
296 GATE_TIM10,
297 GATE_TIM11,
298 GATE_TIM12,
299 GATE_TIM13,
300 GATE_TIM14,
301 GATE_TIM15,
302 GATE_TIM16,
303 GATE_TIM17,
304 GATE_LPTIM1,
305 GATE_LPTIM2,
306 GATE_LPTIM3,
307 GATE_LPTIM4,
308 GATE_LPTIM5,
309 GATE_SPI1,
310 GATE_SPI2,
311 GATE_SPI3,
312 GATE_SPI4,
313 GATE_SPI5,
314 GATE_SPI6,
315 GATE_SPDIFRX,
316 GATE_USART1,
317 GATE_USART2,
318 GATE_USART3,
319 GATE_UART4,
320 GATE_UART5,
321 GATE_USART6,
322 GATE_UART7,
323 GATE_LPUART1,
324 GATE_I2C1,
325 GATE_I2C2,
326 GATE_I2C3,
327 GATE_SAI1,
328 GATE_SAI2,
329 GATE_SAI3,
330 GATE_SAI4,
331 GATE_MDF1,
332 GATE_FDCAN,
333 GATE_HDP,
334 GATE_ADC1,
335 GATE_ADC2,
336 GATE_ETH1MAC,
337 GATE_ETH1,
338 GATE_ETH1TX,
339 GATE_ETH1RX,
340 GATE_ETH1STP,
341 GATE_ETH2MAC,
342 GATE_ETH2,
343 GATE_ETH2STP,
344 GATE_ETH2TX,
345 GATE_ETH2RX,
346 GATE_USBH,
347 GATE_OTG,
348 GATE_USB2PHY1,
349 GATE_USB2PHY2,
350 GATE_STGEN,
351 GATE_SDMMC1,
352 GATE_SDMMC2,
353 GATE_SDMMC3,
354 GATE_LTDC,
355 GATE_CSI,
356 GATE_DCMIPP,
357 GATE_DCMIPSSI,
358 GATE_RNG1,
359 GATE_RNG2,
360 GATE_PKA,
361 GATE_SAES,
362 GATE_HASH1,
363 GATE_HASH2,
364 GATE_CRYP1,
365 GATE_CRYP2,
366 GATE_IWDG1,
367 GATE_IWDG2,
368 GATE_IWDG3,
369 GATE_IWDG4,
370 GATE_WWDG1,
371 GATE_DDRPERFM,
372 GATE_VREF,
373 GATE_DTS,
374 GATE_CRC,
375 GATE_SERC,
376 GATE_I3C1,
377 GATE_I3C2,
378 GATE_I3C3,
379 GATE_NB
380 };
381
382 #define GATE_CFG(_id, _offset, _bit_idx, _offset_clr)\
383 [(_id)] = {\
384 .offset = (_offset),\
385 .bit_idx = (_bit_idx),\
386 .set_clr = (_offset_clr),\
387 }
388
389 static const struct gate_cfg gates_mp21[GATE_NB] = {
390 GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0),
391 GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0),
392 GATE_CFG(GATE_LSI, RCC_LSICR, 0, 0),
393 GATE_CFG(GATE_LSI_RDY, RCC_LSICR, 1, 0),
394 GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0),
395 GATE_CFG(GATE_PLL1, RCC_PLL2CFGR1, 8, 0),
396 GATE_CFG(GATE_PLL1_RDY, RCC_PLL2CFGR1, 24, 0),
397 GATE_CFG(GATE_PLL2, RCC_PLL2CFGR1, 8, 0),
398 GATE_CFG(GATE_PLL2_RDY, RCC_PLL2CFGR1, 24, 0),
399 GATE_CFG(GATE_PLL4, RCC_PLL4CFGR1, 8, 0),
400 GATE_CFG(GATE_PLL4_RDY, RCC_PLL4CFGR1, 24, 0),
401 GATE_CFG(GATE_PLL5, RCC_PLL5CFGR1, 8, 0),
402 GATE_CFG(GATE_PLL5_RDY, RCC_PLL5CFGR1, 24, 0),
403 GATE_CFG(GATE_PLL6, RCC_PLL6CFGR1, 8, 0),
404 GATE_CFG(GATE_PLL6_RDY, RCC_PLL6CFGR1, 24, 0),
405 GATE_CFG(GATE_PLL7, RCC_PLL7CFGR1, 8, 0),
406 GATE_CFG(GATE_PLL7_RDY, RCC_PLL7CFGR1, 24, 0),
407 GATE_CFG(GATE_PLL8, RCC_PLL8CFGR1, 8, 0),
408 GATE_CFG(GATE_PLL8_RDY, RCC_PLL8CFGR1, 24, 0),
409 GATE_CFG(GATE_PLL4_CKREFST, RCC_PLL4CFGR1, 28, 0),
410 GATE_CFG(GATE_PLL5_CKREFST, RCC_PLL5CFGR1, 28, 0),
411 GATE_CFG(GATE_PLL6_CKREFST, RCC_PLL6CFGR1, 28, 0),
412 GATE_CFG(GATE_PLL7_CKREFST, RCC_PLL7CFGR1, 28, 0),
413 GATE_CFG(GATE_PLL8_CKREFST, RCC_PLL8CFGR1, 28, 0),
414 GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 8, 0),
415 GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 8, 0),
416 GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1),
417 GATE_CFG(GATE_HSI_KER, RCC_OCENSETR, 1, 1),
418 GATE_CFG(GATE_MSI, RCC_OCENSETR, 2, 1),
419 GATE_CFG(GATE_MSI_KER, RCC_OCENSETR, 3, 1),
420 GATE_CFG(GATE_HSEDIV2, RCC_OCENSETR, 5, 1),
421 GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1),
422 GATE_CFG(GATE_HSE_KER, RCC_OCENSETR, 9, 1),
423 GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0),
424 GATE_CFG(GATE_MSI_RDY, RCC_OCRDYR, 2, 0),
425 GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0),
426 GATE_CFG(GATE_APB1DIV_RDY, RCC_APB1DIVR, 31, 0),
427 GATE_CFG(GATE_APB2DIV_RDY, RCC_APB2DIVR, 31, 0),
428 GATE_CFG(GATE_APB3DIV_RDY, RCC_APB3DIVR, 31, 0),
429 GATE_CFG(GATE_APB4DIV_RDY, RCC_APB4DIVR, 31, 0),
430 GATE_CFG(GATE_APB5DIV_RDY, RCC_APB5DIVR, 31, 0),
431 GATE_CFG(GATE_APBDBGDIV_RDY, RCC_APBDBGDIVR, 31, 0),
432 GATE_CFG(GATE_TIMG1PRE_RDY, RCC_TIMG1PRER, 31, 0),
433 GATE_CFG(GATE_TIMG2PRE_RDY, RCC_TIMG2PRER, 31, 0),
434 GATE_CFG(GATE_LSMCUDIV_RDY, RCC_LSMCUDIVR, 31, 0),
435 GATE_CFG(GATE_DDRCP, RCC_DDRCPCFGR, 1, 0),
436 GATE_CFG(GATE_DDRCAPB, RCC_DDRCAPBCFGR, 1, 0),
437 GATE_CFG(GATE_DDRPHYCAPB, RCC_DDRPHYCAPBCFGR, 1, 0),
438 GATE_CFG(GATE_DDRPHYC, RCC_DDRPHYCCFGR, 1, 0),
439 GATE_CFG(GATE_DDRCFG, RCC_DDRCFGR, 1, 0),
440 GATE_CFG(GATE_SYSRAM, RCC_SYSRAMCFGR, 1, 0),
441 GATE_CFG(GATE_SRAM1, RCC_SRAM1CFGR, 1, 0),
442 GATE_CFG(GATE_RETRAM, RCC_RETRAMCFGR, 1, 0),
443 GATE_CFG(GATE_BKPSRAM, RCC_BKPSRAMCFGR, 1, 0),
444 GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0),
445 GATE_CFG(GATE_FMC, RCC_FMCCFGR, 1, 0),
446 GATE_CFG(GATE_DBG, RCC_DBGCFGR, 8, 0),
447 GATE_CFG(GATE_DBGMCU, RCC_DBGCFGR, 10, 0),
448 GATE_CFG(GATE_TRACE, RCC_DBGCFGR, 9, 0),
449 GATE_CFG(GATE_STM, RCC_STMCFGR, 1, 0),
450 GATE_CFG(GATE_ETR, RCC_ETRCFGR, 1, 0),
451 GATE_CFG(GATE_GPIOA, RCC_GPIOACFGR, 1, 0),
452 GATE_CFG(GATE_GPIOB, RCC_GPIOBCFGR, 1, 0),
453 GATE_CFG(GATE_GPIOC, RCC_GPIOCCFGR, 1, 0),
454 GATE_CFG(GATE_GPIOD, RCC_GPIODCFGR, 1, 0),
455 GATE_CFG(GATE_GPIOE, RCC_GPIOECFGR, 1, 0),
456 GATE_CFG(GATE_GPIOF, RCC_GPIOFCFGR, 1, 0),
457 GATE_CFG(GATE_GPIOG, RCC_GPIOGCFGR, 1, 0),
458 GATE_CFG(GATE_GPIOH, RCC_GPIOHCFGR, 1, 0),
459 GATE_CFG(GATE_GPIOI, RCC_GPIOICFGR, 1, 0),
460 GATE_CFG(GATE_GPIOZ, RCC_GPIOZCFGR, 1, 0),
461 GATE_CFG(GATE_HPDMA1, RCC_HPDMA1CFGR, 1, 0),
462 GATE_CFG(GATE_HPDMA2, RCC_HPDMA2CFGR, 1, 0),
463 GATE_CFG(GATE_HPDMA3, RCC_HPDMA3CFGR, 1, 0),
464 GATE_CFG(GATE_IPCC1, RCC_IPCC1CFGR, 1, 0),
465 GATE_CFG(GATE_RTC, RCC_RTCCFGR, 1, 0),
466 GATE_CFG(GATE_SYSCPU1, RCC_SYSCPU1CFGR, 1, 0),
467 GATE_CFG(GATE_BSEC, RCC_BSECCFGR, 1, 0),
468 GATE_CFG(GATE_HSIMON, RCC_HSIFMONCR, 15, 0),
469 GATE_CFG(GATE_TIM1, RCC_TIM1CFGR, 1, 0),
470 GATE_CFG(GATE_TIM2, RCC_TIM2CFGR, 1, 0),
471 GATE_CFG(GATE_TIM3, RCC_TIM3CFGR, 1, 0),
472 GATE_CFG(GATE_TIM4, RCC_TIM4CFGR, 1, 0),
473 GATE_CFG(GATE_TIM5, RCC_TIM5CFGR, 1, 0),
474 GATE_CFG(GATE_TIM6, RCC_TIM6CFGR, 1, 0),
475 GATE_CFG(GATE_TIM7, RCC_TIM7CFGR, 1, 0),
476 GATE_CFG(GATE_TIM8, RCC_TIM8CFGR, 1, 0),
477 GATE_CFG(GATE_TIM10, RCC_TIM10CFGR, 1, 0),
478 GATE_CFG(GATE_TIM11, RCC_TIM11CFGR, 1, 0),
479 GATE_CFG(GATE_TIM12, RCC_TIM12CFGR, 1, 0),
480 GATE_CFG(GATE_TIM13, RCC_TIM13CFGR, 1, 0),
481 GATE_CFG(GATE_TIM14, RCC_TIM14CFGR, 1, 0),
482 GATE_CFG(GATE_TIM15, RCC_TIM15CFGR, 1, 0),
483 GATE_CFG(GATE_TIM16, RCC_TIM16CFGR, 1, 0),
484 GATE_CFG(GATE_TIM17, RCC_TIM17CFGR, 1, 0),
485 GATE_CFG(GATE_LPTIM1, RCC_LPTIM1CFGR, 1, 0),
486 GATE_CFG(GATE_LPTIM2, RCC_LPTIM2CFGR, 1, 0),
487 GATE_CFG(GATE_LPTIM3, RCC_LPTIM3CFGR, 1, 0),
488 GATE_CFG(GATE_LPTIM4, RCC_LPTIM4CFGR, 1, 0),
489 GATE_CFG(GATE_LPTIM5, RCC_LPTIM5CFGR, 1, 0),
490 GATE_CFG(GATE_SPI1, RCC_SPI1CFGR, 1, 0),
491 GATE_CFG(GATE_SPI2, RCC_SPI2CFGR, 1, 0),
492 GATE_CFG(GATE_SPI3, RCC_SPI3CFGR, 1, 0),
493 GATE_CFG(GATE_SPI4, RCC_SPI4CFGR, 1, 0),
494 GATE_CFG(GATE_SPI5, RCC_SPI5CFGR, 1, 0),
495 GATE_CFG(GATE_SPI6, RCC_SPI6CFGR, 1, 0),
496 GATE_CFG(GATE_SPDIFRX, RCC_SPDIFRXCFGR, 1, 0),
497 GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0),
498 GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0),
499 GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0),
500 GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0),
501 GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0),
502 GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0),
503 GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0),
504 GATE_CFG(GATE_LPUART1, RCC_LPUART1CFGR, 1, 0),
505 GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0),
506 GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0),
507 GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0),
508 GATE_CFG(GATE_SAI1, RCC_SAI1CFGR, 1, 0),
509 GATE_CFG(GATE_SAI2, RCC_SAI2CFGR, 1, 0),
510 GATE_CFG(GATE_SAI3, RCC_SAI3CFGR, 1, 0),
511 GATE_CFG(GATE_SAI4, RCC_SAI4CFGR, 1, 0),
512 GATE_CFG(GATE_MDF1, RCC_MDF1CFGR, 1, 0),
513 GATE_CFG(GATE_FDCAN, RCC_FDCANCFGR, 1, 0),
514 GATE_CFG(GATE_HDP, RCC_HDPCFGR, 1, 0),
515 GATE_CFG(GATE_ADC1, RCC_ADC1CFGR, 1, 0),
516 GATE_CFG(GATE_ADC2, RCC_ADC2CFGR, 1, 0),
517 GATE_CFG(GATE_ETH1MAC, RCC_ETH1CFGR, 1, 0),
518 GATE_CFG(GATE_ETH1STP, RCC_ETH1CFGR, 4, 0),
519 GATE_CFG(GATE_ETH1, RCC_ETH1CFGR, 5, 0),
520 GATE_CFG(GATE_ETH1TX, RCC_ETH1CFGR, 8, 0),
521 GATE_CFG(GATE_ETH1RX, RCC_ETH1CFGR, 10, 0),
522 GATE_CFG(GATE_ETH2MAC, RCC_ETH2CFGR, 1, 0),
523 GATE_CFG(GATE_ETH2STP, RCC_ETH2CFGR, 4, 0),
524 GATE_CFG(GATE_ETH2, RCC_ETH2CFGR, 5, 0),
525 GATE_CFG(GATE_ETH2TX, RCC_ETH2CFGR, 8, 0),
526 GATE_CFG(GATE_ETH2RX, RCC_ETH2CFGR, 10, 0),
527 GATE_CFG(GATE_OTG, RCC_OTGCFGR, 1, 0),
528 GATE_CFG(GATE_USBH, RCC_USBHCFGR, 1, 0),
529 GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0),
530 GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0),
531 GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0),
532 GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0),
533 GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0),
534 GATE_CFG(GATE_SDMMC3, RCC_SDMMC3CFGR, 1, 0),
535 GATE_CFG(GATE_LTDC, RCC_LTDCCFGR, 1, 0),
536 GATE_CFG(GATE_CSI, RCC_CSICFGR, 1, 0),
537 GATE_CFG(GATE_DCMIPP, RCC_DCMIPPCFGR, 1, 0),
538 GATE_CFG(GATE_DCMIPSSI, RCC_DCMIPSSICFGR, 1, 0),
539 GATE_CFG(GATE_RNG1, RCC_RNG1CFGR, 1, 0),
540 GATE_CFG(GATE_RNG2, RCC_RNG2CFGR, 1, 0),
541 GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0),
542 GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0),
543 GATE_CFG(GATE_HASH1, RCC_HASH1CFGR, 1, 0),
544 GATE_CFG(GATE_HASH2, RCC_HASH2CFGR, 1, 0),
545 GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0),
546 GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0),
547 GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0),
548 GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0),
549 GATE_CFG(GATE_IWDG3, RCC_IWDG3CFGR, 1, 0),
550 GATE_CFG(GATE_IWDG4, RCC_IWDG4CFGR, 1, 0),
551 GATE_CFG(GATE_WWDG1, RCC_WWDG1CFGR, 1, 0),
552 GATE_CFG(GATE_DDRPERFM, RCC_DDRPERFMCFGR, 1, 0),
553 GATE_CFG(GATE_VREF, RCC_VREFCFGR, 1, 0),
554 GATE_CFG(GATE_DTS, RCC_DTSCFGR, 1, 0),
555 GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0),
556 GATE_CFG(GATE_SERC, RCC_SERCCFGR, 1, 0),
557 GATE_CFG(GATE_I3C1, RCC_I3C1CFGR, 1, 0),
558 GATE_CFG(GATE_I3C2, RCC_I3C2CFGR, 1, 0),
559 GATE_CFG(GATE_I3C3, RCC_I3C3CFGR, 1, 0),
560 };
561
562 /*
563 * MUX CONFIG
564 */
565
566 #define _MUX_CFG(_id, _offset, _shift, _width, _rdy)\
567 [(_id)] = {\
568 .offset = (_offset),\
569 .shift = (_shift),\
570 .width = (_width),\
571 .ready = (_rdy),\
572 }
573
574 static const struct mux_cfg parent_mp21[MUX_NB] = {
575 _MUX_CFG(MUX_MUXSEL0, RCC_MUXSELCFGR, 0, 2, GATE_PLL4_CKREFST),
576 _MUX_CFG(MUX_MUXSEL1, RCC_MUXSELCFGR, 4, 2, GATE_PLL5_CKREFST),
577 _MUX_CFG(MUX_MUXSEL2, RCC_MUXSELCFGR, 8, 2, GATE_PLL6_CKREFST),
578 _MUX_CFG(MUX_MUXSEL3, RCC_MUXSELCFGR, 12, 2, GATE_PLL7_CKREFST),
579 _MUX_CFG(MUX_MUXSEL4, RCC_MUXSELCFGR, 16, 2, GATE_PLL8_CKREFST),
580 _MUX_CFG(MUX_MUXSEL5, RCC_MUXSELCFGR, 20, 2, MUX_NO_RDY),
581 _MUX_CFG(MUX_MUXSEL6, RCC_MUXSELCFGR, 24, 2, MUX_NO_RDY),
582 _MUX_CFG(MUX_MUXSEL7, RCC_MUXSELCFGR, 28, 2, MUX_NO_RDY),
583 _MUX_CFG(MUX_XBARSEL, RCC_XBAR0CFGR, 0, 4, MUX_NO_RDY),
584 _MUX_CFG(MUX_RTC, RCC_BDCR, 16, 2, MUX_NO_RDY),
585 _MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 1, MUX_NO_RDY),
586 _MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 1, MUX_NO_RDY),
587 _MUX_CFG(MUX_ADC1, RCC_ADC1CFGR, 12, 1, MUX_NO_RDY),
588 _MUX_CFG(MUX_ADC2, RCC_ADC2CFGR, 12, 2, MUX_NO_RDY),
589 _MUX_CFG(MUX_USB2PHY1, RCC_USB2PHY1CFGR, 15, 1, MUX_NO_RDY),
590 _MUX_CFG(MUX_USB2PHY2, RCC_USB2PHY2CFGR, 15, 1, MUX_NO_RDY),
591 _MUX_CFG(MUX_DTS, RCC_DTSCFGR, 12, 2, MUX_NO_RDY),
592 };
593
594 /*
595 * DIV CONFIG
596 */
597
598 static const struct div_table_cfg apb_div_table[] = {
599 { .val = 0, .div = 1 },
600 { .val = 1, .div = 2 },
601 { .val = 2, .div = 4 },
602 { .val = 3, .div = 8 },
603 { .val = 4, .div = 16 },
604 { .val = 5, .div = 16 },
605 { .val = 6, .div = 16 },
606 { .val = 7, .div = 16 },
607 /* .div = 0 termination cell */
608 { }
609 };
610
611 #define _DIV_CFG(_id, _offset, _shift, _width, _flags, _table, _ready)\
612 [(_id)] = {\
613 .offset = (_offset),\
614 .shift = (_shift),\
615 .width = (_width),\
616 .flags = (_flags),\
617 .table = (_table),\
618 .ready = (_ready),\
619 }
620
621 static const struct div_cfg dividers_mp21[DIV_NB] = {
622 _DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, DIV_NO_RDY),
623 _DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table,
624 GATE_APB1DIV_RDY),
625 _DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table,
626 GATE_APB2DIV_RDY),
627 _DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table,
628 GATE_APB3DIV_RDY),
629 _DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table,
630 GATE_APB4DIV_RDY),
631 _DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table,
632 GATE_APB5DIV_RDY),
633 _DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table,
634 GATE_APBDBGDIV_RDY),
635 _DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, GATE_LSMCUDIV_RDY),
636 };
637
638 enum stm32_osc {
639 OSC_HSI,
640 OSC_HSE,
641 OSC_MSI,
642 OSC_LSI,
643 OSC_LSE,
644 NB_OSCILLATOR
645 };
646
647 struct clk_stm32_bypass {
648 uint16_t offset;
649 uint8_t bit_byp;
650 uint8_t bit_digbyp;
651 };
652
653 struct clk_stm32_css {
654 uint16_t offset;
655 uint8_t bit_css;
656 };
657
658 struct clk_stm32_drive {
659 uint16_t offset;
660 uint8_t drv_shift;
661 uint8_t drv_width;
662 uint8_t drv_default;
663 };
664
665 struct clk_oscillator_data {
666 const char *name;
667 unsigned long frequency;
668 uint16_t gate_id;
669 struct clk_stm32_bypass *bypass;
670 struct clk_stm32_css *css;
671 struct clk_stm32_drive *drive;
672 };
673
674 #define BYPASS(_offset, _bit_byp, _bit_digbyp) \
675 (&(struct clk_stm32_bypass){\
676 .offset = (_offset),\
677 .bit_byp = (_bit_byp),\
678 .bit_digbyp = (_bit_digbyp),\
679 })
680
681 #define CSS(_offset, _bit_css) \
682 (&(struct clk_stm32_css){\
683 .offset = (_offset),\
684 .bit_css = (_bit_css),\
685 })
686
687 #define DRIVE(_offset, _shift, _width, _default) \
688 (&(struct clk_stm32_drive){\
689 .offset = (_offset),\
690 .drv_shift = (_shift),\
691 .drv_width = (_width),\
692 .drv_default = (_default),\
693 })
694
695 #define OSCILLATOR(idx_osc, _name, _gate_id, _bypass, _css, _drive) \
696 [(idx_osc)] = (struct clk_oscillator_data){\
697 .name = (_name),\
698 .gate_id = (_gate_id),\
699 .bypass = (_bypass),\
700 .css = (_css),\
701 .drive = (_drive),\
702 }
703
704 static struct clk_oscillator_data stm32mp21_osc_data[NB_OSCILLATOR] = {
705 OSCILLATOR(OSC_HSI, "clk-hsi", GATE_HSI,
706 NULL, NULL, NULL),
707
708 OSCILLATOR(OSC_LSI, "clk-lsi", GATE_LSI,
709 NULL, NULL, NULL),
710
711 OSCILLATOR(OSC_MSI, "clk-msi", GATE_MSI,
712 NULL, NULL, NULL),
713
714 OSCILLATOR(OSC_LSE, "clk-lse", GATE_LSE,
715 BYPASS(RCC_BDCR, RCC_BDCR_LSEBYP_BIT,
716 RCC_BDCR_LSEDIGBYP_BIT),
717 CSS(RCC_BDCR, RCC_BDCR_LSECSSON_BIT),
718 DRIVE(RCC_BDCR, RCC_BDCR_LSEDRV_SHIFT,
719 RCC_BDCR_LSEDRV_WIDTH, LSEDRV_MEDIUM_HIGH)),
720
721 OSCILLATOR(OSC_HSE, "clk-hse", GATE_HSE,
722 BYPASS(RCC_OCENSETR, RCC_OCENSETR_HSEBYP_BIT,
723 RCC_OCENSETR_HSEDIGBYP_BIT),
724 CSS(RCC_OCENSETR, RCC_OCENSETR_HSECSSON_BIT),
725 NULL),
726 };
727
stm32_rcc_has_access_by_id(int id)728 static bool stm32_rcc_has_access_by_id(int id)
729 {
730 struct clk_stm32_priv *priv = clk_stm32_get_priv();
731 uintptr_t rcc_base = priv->base;
732 uint32_t cid_reg_value = 0;
733
734 cid_reg_value = io_read32(rcc_base + RCC_R0CIDCFGR + 0x8 * id);
735
736 if (!(cid_reg_value & RCC_CIDCFGR_CFEN))
737 return true;
738
739 /*
740 * Check conditions for semaphore mode, which does not
741 * take into account static CID.
742 */
743 if (cid_reg_value & RCC_CIDCFGR_SEM_EN) {
744 /* Static CID is irrelevant if semaphore mode */
745 return cid_reg_value & BIT(RIF_CID1 + RCC_SEMWL_SHIFT);
746 }
747
748 /*
749 * Coherency check with the CID configuration
750 */
751 if (((cid_reg_value & RCC_CIDCFGR_SCID_MASK) >>
752 RCC_CIDCFGR_SCID_SHIFT) != RIF_CID1)
753 return false;
754
755 return true;
756 }
757
clk_oscillator_get_data(unsigned int osc_id)758 static struct clk_oscillator_data *clk_oscillator_get_data(unsigned int osc_id)
759 {
760 assert(osc_id < ARRAY_SIZE(stm32mp21_osc_data));
761
762 return &stm32mp21_osc_data[osc_id];
763 }
764
clk_stm32_get_rate_oscillator(unsigned int osc_id)765 static unsigned long clk_stm32_get_rate_oscillator(unsigned int osc_id)
766 {
767 struct clk_stm32_priv *priv = clk_stm32_get_priv();
768 struct stm32_clk_platdata *pdata = priv->pdata;
769 struct stm32_osci_dt_cfg *osci = &pdata->osci[osc_id];
770
771 return osci->freq;
772 }
773
clk_stm32_pll_get_oscillator_rate(unsigned int sel)774 static unsigned long clk_stm32_pll_get_oscillator_rate(unsigned int sel)
775 {
776 unsigned int osc[] = { OSC_HSI, OSC_HSE, OSC_MSI };
777
778 assert(sel < ARRAY_SIZE(osc));
779
780 return clk_stm32_get_rate_oscillator(osc[sel]);
781 }
782
clk_oscillator_set_bypass(struct clk_stm32_priv * priv,struct clk_oscillator_data * osc_data,bool digbyp,bool bypass)783 static void clk_oscillator_set_bypass(struct clk_stm32_priv *priv,
784 struct clk_oscillator_data *osc_data,
785 bool digbyp, bool bypass)
786 {
787 struct clk_stm32_bypass *bypass_data = osc_data->bypass;
788 uintptr_t address = 0;
789
790 if (!bypass_data)
791 return;
792
793 address = priv->base + bypass_data->offset;
794
795 if (digbyp)
796 io_setbits32(address, BIT(bypass_data->bit_digbyp));
797
798 if (bypass || digbyp)
799 io_setbits32(address, BIT(bypass_data->bit_byp));
800 }
801
clk_oscillator_set_css(struct clk_stm32_priv * priv,struct clk_oscillator_data * osc_data,bool css)802 static void clk_oscillator_set_css(struct clk_stm32_priv *priv,
803 struct clk_oscillator_data *osc_data,
804 bool css)
805 {
806 struct clk_stm32_css *css_data = osc_data->css;
807
808 if (css_data && css)
809 io_setbits32(priv->base + css_data->offset,
810 BIT(css_data->bit_css));
811 }
812
clk_oscillator_set_drive(struct clk_stm32_priv * priv,struct clk_oscillator_data * osc_data,uint8_t lsedrv)813 static void clk_oscillator_set_drive(struct clk_stm32_priv *priv,
814 struct clk_oscillator_data *osc_data,
815 uint8_t lsedrv)
816 {
817 struct clk_stm32_drive *drive_data = osc_data->drive;
818 uintptr_t address = 0;
819 uint32_t mask = 0;
820 uint32_t value = 0;
821
822 if (!drive_data)
823 return;
824
825 address = priv->base + drive_data->offset;
826
827 mask = SHIFT_U32(BIT(drive_data->drv_width) - 1, drive_data->drv_shift);
828
829 /*
830 * Warning: not recommended to switch directly from "high drive"
831 * to "medium low drive", and vice-versa.
832 */
833 value = (io_read32(address) & mask) >> drive_data->drv_shift;
834
835 while (value != lsedrv) {
836 if (value > lsedrv)
837 value--;
838 else
839 value++;
840
841 io_clrsetbits32(address, mask,
842 SHIFT_U32(value, drive_data->drv_shift));
843 }
844 }
845
stm32_enable_oscillator_hse(struct clk_stm32_priv * priv,struct stm32_clk_platdata * pdata)846 static void stm32_enable_oscillator_hse(struct clk_stm32_priv *priv,
847 struct stm32_clk_platdata *pdata)
848 {
849 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_HSE);
850 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE];
851
852 if (!stm32_rcc_has_access_by_id(RCC_RIF_OSCILLATORS))
853 return;
854
855 if (!osci->freq)
856 return;
857
858 clk_oscillator_set_bypass(priv, osc_data, osci->digbyp, osci->bypass);
859
860 /* Enable clock and wait ready bit */
861 if (stm32_gate_rdy_enable(osc_data->gate_id))
862 panic("timeout to enable hse clock");
863
864 clk_oscillator_set_css(priv, osc_data, osci->css);
865 }
866
stm32_enable_oscillator_lse(struct clk_stm32_priv * priv,struct stm32_clk_platdata * pdata)867 static void stm32_enable_oscillator_lse(struct clk_stm32_priv *priv,
868 struct stm32_clk_platdata *pdata)
869 {
870 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE);
871 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE];
872
873 if (!stm32_rcc_has_access_by_id(RCC_RIF_OSCILLATORS))
874 return;
875
876 if (!osci->freq)
877 return;
878
879 if (stm32_gate_is_enabled(osc_data->gate_id))
880 return;
881
882 clk_oscillator_set_bypass(priv, osc_data, osci->digbyp, osci->bypass);
883
884 clk_oscillator_set_drive(priv, osc_data, osci->drive);
885
886 /* Enable LSE clock, but don't wait ready bit */
887 stm32_gate_enable(osc_data->gate_id);
888 }
889
stm32_enable_oscillator_lsi(struct clk_stm32_priv * priv __unused,struct stm32_clk_platdata * pdata)890 static void stm32_enable_oscillator_lsi(struct clk_stm32_priv *priv __unused,
891 struct stm32_clk_platdata *pdata)
892 {
893 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSI);
894 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSI];
895
896 if (!stm32_rcc_has_access_by_id(RCC_RIF_OSCILLATORS))
897 return;
898
899 if (!osci->freq)
900 return;
901
902 /* Enable clock and wait ready bit */
903 if (stm32_gate_rdy_enable(osc_data->gate_id))
904 panic("timeout to enable lsi clock");
905 }
906
stm32_enable_oscillator_msi(struct clk_stm32_priv * priv __unused,struct stm32_clk_platdata * pdata)907 static void stm32_enable_oscillator_msi(struct clk_stm32_priv *priv __unused,
908 struct stm32_clk_platdata *pdata)
909 {
910 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_MSI);
911 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_MSI];
912
913 if (!stm32_rcc_has_access_by_id(RCC_RIF_OSCILLATORS))
914 return;
915
916 if (!osci->freq)
917 return;
918
919 /* Enable clock and wait ready bit */
920 if (stm32_gate_rdy_enable(osc_data->gate_id))
921 panic("timeout to enable msi clock");
922 }
923
stm32_clk_oscillators_lse_set_css(struct clk_stm32_priv * priv,struct stm32_clk_platdata * pdata)924 static void stm32_clk_oscillators_lse_set_css(struct clk_stm32_priv *priv,
925 struct stm32_clk_platdata *pdata)
926
927 {
928 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE);
929 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE];
930
931 if (stm32_rcc_has_access_by_id(RCC_RIF_OSCILLATORS))
932 clk_oscillator_set_css(priv, osc_data, osci->css);
933 }
934
935 static int
stm32_clk_oscillators_wait_lse_ready(struct clk_stm32_priv * priv __unused,struct stm32_clk_platdata * pdata)936 stm32_clk_oscillators_wait_lse_ready(struct clk_stm32_priv *priv __unused,
937 struct stm32_clk_platdata *pdata)
938 {
939 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE);
940 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE];
941 int ret = 0;
942
943 if (stm32_rcc_has_access_by_id(RCC_RIF_OSCILLATORS)) {
944 if (osci->freq &&
945 stm32_gate_wait_ready(osc_data->gate_id, true))
946 ret = -1;
947 }
948
949 return ret;
950 }
951
stm32_clk_oscillators_enable(struct clk_stm32_priv * priv,struct stm32_clk_platdata * pdata)952 static void stm32_clk_oscillators_enable(struct clk_stm32_priv *priv,
953 struct stm32_clk_platdata *pdata)
954 {
955 stm32_enable_oscillator_hse(priv, pdata);
956 stm32_enable_oscillator_lse(priv, pdata);
957 stm32_enable_oscillator_lsi(priv, pdata);
958 stm32_enable_oscillator_msi(priv, pdata);
959 }
960
961 enum stm32_pll_id {
962 PLL1_ID,
963 PLL2_ID,
964 PLL3_ID,
965 PLL4_ID,
966 PLL5_ID,
967 PLL6_ID,
968 PLL7_ID,
969 PLL8_ID,
970 PLL_NB
971 };
972
973 /* PLL configuration registers offsets from RCC_PLLxCFGR1 */
974 #define RCC_OFFSET_PLLXCFGR1 0x00
975 #define RCC_OFFSET_PLLXCFGR2 0x04
976 #define RCC_OFFSET_PLLXCFGR3 0x08
977 #define RCC_OFFSET_PLLXCFGR4 0x0C
978 #define RCC_OFFSET_PLLXCFGR5 0x10
979 #define RCC_OFFSET_PLLXCFGR6 0x18
980 #define RCC_OFFSET_PLLXCFGR7 0x1C
981
982 struct stm32_clk_pll {
983 uint16_t gate_id;
984 uint16_t mux_id;
985 uint16_t reg_pllxcfgr1;
986 };
987
988 #define CLK_PLL_CFG(_idx, _gate_id, _mux_id, _reg)\
989 [(_idx)] = {\
990 .gate_id = (_gate_id),\
991 .mux_id = (_mux_id),\
992 .reg_pllxcfgr1 = (_reg),\
993 }
994
995 static const struct stm32_clk_pll stm32mp21_clk_pll[PLL_NB] = {
996 CLK_PLL_CFG(PLL1_ID, GATE_PLL1, MUX_MUXSEL5, 0),
997 CLK_PLL_CFG(PLL2_ID, GATE_PLL2, MUX_MUXSEL6, RCC_PLL2CFGR1),
998 CLK_PLL_CFG(PLL4_ID, GATE_PLL4, MUX_MUXSEL0, RCC_PLL4CFGR1),
999 CLK_PLL_CFG(PLL5_ID, GATE_PLL5, MUX_MUXSEL1, RCC_PLL5CFGR1),
1000 CLK_PLL_CFG(PLL6_ID, GATE_PLL6, MUX_MUXSEL2, RCC_PLL6CFGR1),
1001 CLK_PLL_CFG(PLL7_ID, GATE_PLL7, MUX_MUXSEL3, RCC_PLL7CFGR1),
1002 CLK_PLL_CFG(PLL8_ID, GATE_PLL8, MUX_MUXSEL4, RCC_PLL8CFGR1),
1003 };
1004
clk_stm32_pll_data(unsigned int idx)1005 static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx)
1006 {
1007 assert(idx < ARRAY_SIZE(stm32mp21_clk_pll));
1008
1009 return &stm32mp21_clk_pll[idx];
1010 }
1011
stm32_clk_parse_oscillator_fdt(const void * fdt,int node,const char * name,struct stm32_osci_dt_cfg * osci)1012 static int stm32_clk_parse_oscillator_fdt(const void *fdt, int node,
1013 const char *name,
1014 struct stm32_osci_dt_cfg *osci)
1015 {
1016 int subnode = 0;
1017
1018 /* default value when oscillator is not found */
1019 osci->freq = 0;
1020
1021 fdt_for_each_subnode(subnode, fdt, node) {
1022 const char *cchar = NULL;
1023 const fdt32_t *cuint = NULL;
1024 int ret = 0;
1025
1026 cchar = fdt_get_name(fdt, subnode, &ret);
1027 if (!cchar)
1028 return -1;
1029
1030 if (strncmp(cchar, name, (size_t)ret))
1031 continue;
1032
1033 if (fdt_get_status(fdt, subnode) == DT_STATUS_DISABLED)
1034 return 0;
1035
1036 cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret);
1037 if (!cuint)
1038 return -1;
1039
1040 osci->freq = fdt32_to_cpu(*cuint);
1041
1042 if (fdt_getprop(fdt, subnode, "st,bypass", NULL))
1043 osci->bypass = true;
1044
1045 if (fdt_getprop(fdt, subnode, "st,digbypass", NULL))
1046 osci->digbyp = true;
1047
1048 if (fdt_getprop(fdt, subnode, "st,css", NULL))
1049 osci->css = true;
1050
1051 osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive",
1052 LSEDRV_MEDIUM_HIGH);
1053
1054 return 0;
1055 }
1056
1057 return 0;
1058 }
1059
stm32_clk_get_oscillator_name(enum stm32_osc id)1060 static const char *stm32_clk_get_oscillator_name(enum stm32_osc id)
1061 {
1062 if (id < NB_OSCILLATOR)
1063 return stm32mp21_osc_data[id].name;
1064
1065 return NULL;
1066 }
1067
stm32_clk_parse_fdt_all_oscillator(const void * fdt,int node __unused,struct stm32_clk_platdata * pdata)1068 static int stm32_clk_parse_fdt_all_oscillator(const void *fdt,
1069 int node __unused,
1070 struct stm32_clk_platdata *pdata)
1071 {
1072 int fdt_err = 0;
1073 size_t i = 0;
1074 int osc_node = 0;
1075
1076 osc_node = fdt_path_offset(fdt, "/clocks");
1077 if (osc_node < 0)
1078 return -FDT_ERR_NOTFOUND;
1079
1080 for (i = 0; i < pdata->nosci; i++) {
1081 const char *name = NULL;
1082
1083 name = stm32_clk_get_oscillator_name((enum stm32_osc)i);
1084 if (!name)
1085 continue;
1086
1087 fdt_err = stm32_clk_parse_oscillator_fdt(fdt, osc_node, name,
1088 &pdata->osci[i]);
1089 if (fdt_err < 0)
1090 panic();
1091 }
1092
1093 return 0;
1094 }
1095
clk_stm32_parse_pll_fdt(const void * fdt,int subnode,struct stm32_pll_dt_cfg * pll)1096 static int clk_stm32_parse_pll_fdt(const void *fdt, int subnode,
1097 struct stm32_pll_dt_cfg *pll)
1098 {
1099 const fdt32_t *cuint = NULL;
1100 int subnode_pll = 0;
1101 int err = 0;
1102
1103 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL);
1104 if (!cuint)
1105 return 0;
1106
1107 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
1108 if (subnode_pll < 0)
1109 return -FDT_ERR_NOTFOUND;
1110
1111 if (fdt_read_uint32_array(fdt, subnode_pll, "cfg", pll->cfg, PLLCFG_NB))
1112 panic("cfg property is mandatory");
1113
1114 err = fdt_read_uint32_array(fdt, subnode_pll, "csg", pll->csg,
1115 PLLCSG_NB);
1116
1117 pll->csg_enabled = (err == 0);
1118
1119 if (err == -FDT_ERR_NOTFOUND)
1120 err = 0;
1121
1122 if (err)
1123 return err;
1124
1125 pll->enabled = true;
1126
1127 pll->frac = fdt_read_uint32_default(fdt, subnode_pll, "frac", 0);
1128
1129 if (fdt_read_uint32(fdt, subnode_pll, "src", &pll->src))
1130 panic("src property is mandatory");
1131
1132 return 0;
1133 }
1134
1135 #define RCC_PLL_NAME_SIZE 20
1136
stm32_clk_parse_fdt_all_pll(const void * fdt,int node,struct stm32_clk_platdata * pdata)1137 static int stm32_clk_parse_fdt_all_pll(const void *fdt, int node,
1138 struct stm32_clk_platdata *pdata)
1139 {
1140 unsigned int i = 0;
1141
1142 for (i = 0; i < pdata->npll; i++) {
1143 struct stm32_pll_dt_cfg *pll = pdata->pll + i;
1144 char name[RCC_PLL_NAME_SIZE] = { };
1145 int subnode = 0;
1146
1147 snprintf(name, sizeof(name), "st,pll-%u", i + 1);
1148
1149 subnode = fdt_subnode_offset(fdt, node, name);
1150 if (subnode < 0)
1151 continue;
1152
1153 /* No PLL3 in the STM32MP21 SOC */
1154 if (i == PLL3_ID)
1155 panic("invalid PLL3");
1156
1157 if (clk_stm32_parse_pll_fdt(fdt, subnode, pll))
1158 panic();
1159 }
1160
1161 return 0;
1162 }
1163
stm32_clk_parse_fdt_opp(const void * fdt,int node,const char * opp_name,struct stm32_clk_opp_cfg * opp_cfg)1164 static int stm32_clk_parse_fdt_opp(const void *fdt, int node,
1165 const char *opp_name,
1166 struct stm32_clk_opp_cfg *opp_cfg)
1167 {
1168 int subnode = 0;
1169 int nb_opp = 0;
1170 int ret = 0;
1171
1172 node = fdt_subnode_offset(fdt, node, opp_name);
1173 if (node == -FDT_ERR_NOTFOUND)
1174 return 0;
1175
1176 if (node < 0)
1177 return node;
1178
1179 fdt_for_each_subnode(subnode, fdt, node) {
1180 assert(nb_opp <= MAX_OPP);
1181
1182 if (fdt_read_uint32(fdt, subnode, "hz", &opp_cfg->frq))
1183 panic("hz property is mandatory");
1184
1185 ret = clk_stm32_parse_pll_fdt(fdt, subnode, &opp_cfg->pll_cfg);
1186 if (ret < 0)
1187 return ret;
1188
1189 opp_cfg++;
1190 nb_opp++;
1191 }
1192
1193 return 0;
1194 }
1195
stm32_clk_parse_fdt_all_opp(const void * fdt,int node,struct stm32_clk_platdata * pdata)1196 static int stm32_clk_parse_fdt_all_opp(const void *fdt, int node,
1197 struct stm32_clk_platdata *pdata)
1198 {
1199 struct stm32_clk_opp_dt_cfg *opp = pdata->opp;
1200
1201 node = fdt_subnode_offset(fdt, node, "st,clk_opp");
1202 if (node == -FDT_ERR_NOTFOUND)
1203 return 0;
1204
1205 if (node < 0)
1206 return node;
1207
1208 return stm32_clk_parse_fdt_opp(fdt, node, "st,ck_cpu1", opp->cpu1_opp);
1209 }
1210
stm32_clk_parse_fdt(const void * fdt,int node,struct stm32_clk_platdata * pdata)1211 static int stm32_clk_parse_fdt(const void *fdt, int node,
1212 struct stm32_clk_platdata *pdata)
1213 {
1214 const fdt32_t *cuint = NULL;
1215 unsigned int i = 0;
1216 int lenp = 0;
1217 int err = 0;
1218
1219 err = stm32_clk_parse_fdt_all_oscillator(fdt, node, pdata);
1220 if (err)
1221 return err;
1222
1223 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata);
1224 if (err)
1225 return err;
1226
1227 err = stm32_clk_parse_fdt_all_opp(fdt, node, pdata);
1228 if (err)
1229 return err;
1230
1231 err = clk_stm32_parse_fdt_by_name(fdt, node, "st,busclk",
1232 pdata->busclk,
1233 &pdata->nbusclk);
1234 if (err)
1235 return err;
1236
1237 err = clk_stm32_parse_fdt_by_name(fdt, node, "st,flexgen",
1238 pdata->flexgen,
1239 &pdata->nflexgen);
1240 if (err)
1241 return err;
1242
1243 err = clk_stm32_parse_fdt_by_name(fdt, node, "st,kerclk",
1244 pdata->kernelclk,
1245 &pdata->nkernelclk);
1246 if (err)
1247 return err;
1248
1249 pdata->c1msrd = fdt_read_uint32_default(fdt, node, "st,c1msrd", 0);
1250
1251 if (fdt_getprop(fdt, node, "st,safe_rst", NULL))
1252 pdata->safe_rst = true;
1253
1254 pdata->rcc_base = stm32_rcc_base();
1255
1256 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp);
1257 if (lenp < 0) {
1258 if (lenp != -FDT_ERR_NOTFOUND)
1259 return lenp;
1260
1261 lenp = 0;
1262 DMSG("No RIF configuration available");
1263 }
1264
1265 pdata->nb_res = (unsigned int)(lenp / sizeof(uint32_t));
1266
1267 assert(pdata->nb_res <= RCC_NB_RIF_RES);
1268
1269 pdata->conf_data.cid_confs = calloc(RCC_NB_RIF_RES, sizeof(uint32_t));
1270 pdata->conf_data.sec_conf = calloc(RCC_NB_CONFS, sizeof(uint32_t));
1271 pdata->conf_data.priv_conf = calloc(RCC_NB_CONFS, sizeof(uint32_t));
1272 pdata->conf_data.lock_conf = calloc(RCC_NB_CONFS, sizeof(uint32_t));
1273 pdata->conf_data.access_mask = calloc(RCC_NB_CONFS, sizeof(uint32_t));
1274 if (!pdata->conf_data.cid_confs || !pdata->conf_data.sec_conf ||
1275 !pdata->conf_data.priv_conf || !pdata->conf_data.access_mask ||
1276 !pdata->conf_data.lock_conf)
1277 panic("Missing memory capacity for RCC RIF configuration");
1278
1279 for (i = 0; i < pdata->nb_res; i++)
1280 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), &pdata->conf_data,
1281 RCC_NB_RIF_RES);
1282
1283 return 0;
1284 }
1285
stm32mp2_a35_ss_on_bypass(void)1286 static void stm32mp2_a35_ss_on_bypass(void)
1287 {
1288 uint64_t timeout = 0;
1289 uint32_t chgclkreq = stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ);
1290
1291 if (chgclkreq & CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK) {
1292 /* Nothing to do, clock source is already set on bypass clock */
1293 return;
1294 }
1295
1296 /*
1297 * for clkext2f frequency at 400MHZ, the default flexgen63 config,
1298 * divider by 2 is required with ARM_DIVSEL=0
1299 */
1300 if (chgclkreq & CA35SS_SSC_CHGCLKREQ_ARM_DIVSEL) {
1301 stm32mp_syscfg_write(CA35SS_SSC_CHGCLKREQ,
1302 0U,
1303 CA35SS_SSC_CHGCLKREQ_ARM_DIVSEL);
1304 timeout = timeout_init_us(CLKSRC_TIMEOUT);
1305 while (!timeout_elapsed(timeout))
1306 if (!(stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ) &
1307 CA35SS_SSC_CHGCLKREQ_ARM_DIVSELACK))
1308 break;
1309 if (stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ) &
1310 CA35SS_SSC_CHGCLKREQ_ARM_DIVSELACK)
1311 panic("Cannot set div on A35 bypass clock");
1312 }
1313
1314 stm32mp_syscfg_write(CA35SS_SSC_CHGCLKREQ,
1315 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ,
1316 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_MASK);
1317
1318 timeout = timeout_init_us(CLKSRC_TIMEOUT);
1319 while (!timeout_elapsed(timeout))
1320 if (stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ) &
1321 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK)
1322 break;
1323
1324 if (!(stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ) &
1325 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK))
1326 panic("Cannot switch A35 to bypass clock");
1327
1328 stm32mp_syscfg_write(CA35SS_SSC_PLL_EN,
1329 0,
1330 CA35SS_SSC_PLL_EN_NRESET_SWPLL_MASK);
1331 }
1332
stm32mp2_clk_xbar_on_hsi(struct clk_stm32_priv * priv)1333 static void stm32mp2_clk_xbar_on_hsi(struct clk_stm32_priv *priv)
1334 {
1335 uintptr_t xbar0cfgr = priv->base + RCC_XBAR0CFGR;
1336 uint32_t i = 0;
1337
1338 for (i = 0; i < XBAR_ROOT_CHANNEL_NB; i++)
1339 io_clrsetbits32(xbar0cfgr + (0x4 * i),
1340 RCC_XBAR0CFGR_XBAR0SEL_MASK, XBAR_SRC_HSI);
1341 }
1342
stm32mp2_a35_pll1_start(void)1343 static int stm32mp2_a35_pll1_start(void)
1344 {
1345 uint64_t timeout = 0;
1346
1347 stm32mp_syscfg_write(CA35SS_SSC_PLL_EN,
1348 CA35SS_SSC_PLL_EN_PLL_EN,
1349 CA35SS_SSC_PLL_EN_PLL_EN);
1350
1351 /* Wait PLL lock */
1352 timeout = timeout_init_us(PLLRDY_TIMEOUT);
1353 while (!timeout_elapsed(timeout))
1354 if (stm32mp_syscfg_read(CA35SS_SSC_PLL_EN) &
1355 CA35SS_SSC_PLL_EN_LOCKP_MASK)
1356 break;
1357
1358 if (!(stm32mp_syscfg_read(CA35SS_SSC_PLL_EN) &
1359 CA35SS_SSC_PLL_EN_LOCKP_MASK)) {
1360 EMSG("PLL1 not locked");
1361 return -1;
1362 }
1363
1364 /* De-assert reset on PLL output clock path */
1365 stm32mp_syscfg_write(CA35SS_SSC_PLL_EN,
1366 CA35SS_SSC_PLL_EN_NRESET_SWPLL,
1367 CA35SS_SSC_PLL_EN_NRESET_SWPLL_MASK);
1368
1369 /* Switch CPU clock to PLL clock */
1370 stm32mp_syscfg_write(CA35SS_SSC_CHGCLKREQ,
1371 0,
1372 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_MASK);
1373
1374 /* Wait for clock change acknowledge */
1375 timeout = timeout_init_us(CLKSRC_TIMEOUT);
1376 while (!timeout_elapsed(timeout))
1377 if (!(stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ) &
1378 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK))
1379 break;
1380
1381 if (stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ) &
1382 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK) {
1383 EMSG("A35 switch to PLL1 failed");
1384 return -1;
1385 }
1386
1387 return 0;
1388 }
1389
stm32mp2_a35_pll1_config(uint32_t fbdiv,uint32_t refdiv,uint32_t postdiv1,uint32_t postdiv2)1390 static void stm32mp2_a35_pll1_config(uint32_t fbdiv, uint32_t refdiv,
1391 uint32_t postdiv1, uint32_t postdiv2)
1392 {
1393 stm32mp_syscfg_write(CA35SS_SSC_PLL_FREQ1,
1394 SHIFT_U32(refdiv,
1395 CA35SS_SSC_PLL_FREQ1_REFDIV_SHIFT) |
1396 SHIFT_U32(fbdiv, CA35SS_SSC_PLL_FREQ1_FBDIV_SHIFT),
1397 CA35SS_SSC_PLL_FREQ1_MASK);
1398
1399 stm32mp_syscfg_write(CA35SS_SSC_PLL_FREQ2,
1400 SHIFT_U32(postdiv1,
1401 CA35SS_SSC_PLL_FREQ2_POSTDIV1_SHIFT) |
1402 SHIFT_U32(postdiv2,
1403 CA35SS_SSC_PLL_FREQ2_POSTDIV2_SHIFT),
1404 CA35SS_SSC_PLL_FREQ2_MASK);
1405 }
1406
clk_stm32_pll_config_output(struct clk_stm32_priv * priv,const struct stm32_clk_pll * pll,uint32_t pllsrc,uint32_t * pllcfg,uint32_t fracv)1407 static void clk_stm32_pll_config_output(struct clk_stm32_priv *priv,
1408 const struct stm32_clk_pll *pll,
1409 uint32_t pllsrc,
1410 uint32_t *pllcfg,
1411 uint32_t fracv)
1412 {
1413 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
1414 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2;
1415 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;
1416 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;
1417 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6;
1418 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7;
1419 int sel = (pllsrc & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
1420 unsigned long refclk = clk_stm32_pll_get_oscillator_rate(sel);
1421
1422 if (!fracv) {
1423 /* PLL in integer mode */
1424
1425 /*
1426 * No need to check max clock, as oscillator reference clocks
1427 * will always be less than 1.2GHz
1428 */
1429 if (refclk < PLL_REFCLK_MIN)
1430 panic();
1431
1432 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK);
1433 io_clrbits32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN);
1434 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_DACEN);
1435 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS);
1436 io_setbits32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST);
1437 } else {
1438 /* PLL in frac mode */
1439
1440 /*
1441 * No need to check max clock, as oscillator reference clocks
1442 * will always be less than 1.2GHz
1443 */
1444 if (refclk < PLL_FRAC_REFCLK_MIN)
1445 panic();
1446
1447 io_clrsetbits32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK,
1448 fracv & RCC_PLLxCFGR3_FRACIN_MASK);
1449 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS);
1450 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN);
1451 }
1452
1453 assert(pllcfg[REFDIV]);
1454
1455 io_clrsetbits32(pllxcfgr2, RCC_PLLxCFGR2_FBDIV_MASK,
1456 SHIFT_U32(pllcfg[FBDIV], RCC_PLLxCFGR2_FBDIV_SHIFT) &
1457 RCC_PLLxCFGR2_FBDIV_MASK);
1458 io_clrsetbits32(pllxcfgr2, RCC_PLLxCFGR2_FREFDIV_MASK,
1459 pllcfg[REFDIV] & RCC_PLLxCFGR2_FREFDIV_MASK);
1460 io_clrsetbits32(pllxcfgr6, RCC_PLLxCFGR6_POSTDIV1_MASK,
1461 pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK);
1462 io_clrsetbits32(pllxcfgr7, RCC_PLLxCFGR7_POSTDIV2_MASK,
1463 pllcfg[POSTDIV2] & RCC_PLLxCFGR7_POSTDIV2_MASK);
1464
1465 if (!pllcfg[POSTDIV1] || !pllcfg[POSTDIV2]) {
1466 /* Bypass mode */
1467 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS);
1468 io_clrbits32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN);
1469 } else {
1470 io_clrbits32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS);
1471 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN);
1472 }
1473 }
1474
clk_stm32_pll_config_csg(struct clk_stm32_priv * priv,const struct stm32_clk_pll * pll,uint32_t * csg)1475 static void clk_stm32_pll_config_csg(struct clk_stm32_priv *priv,
1476 const struct stm32_clk_pll *pll,
1477 uint32_t *csg)
1478 {
1479 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
1480 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;
1481 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;
1482 uintptr_t pllxcfgr5 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR5;
1483
1484 io_clrsetbits32(pllxcfgr5, RCC_PLLxCFGR5_DIVVAL_MASK,
1485 csg[DIVVAL] & RCC_PLLxCFGR5_DIVVAL_MASK);
1486 io_clrsetbits32(pllxcfgr5, RCC_PLLxCFGR5_SPREAD_MASK,
1487 SHIFT_U32(csg[SPREAD], RCC_PLLxCFGR5_SPREAD_SHIFT) &
1488 RCC_PLLxCFGR5_SPREAD_MASK);
1489
1490 if (csg[DOWNSPREAD])
1491 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD);
1492 else
1493 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD);
1494
1495 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS);
1496
1497 io_clrbits32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN);
1498 udelay(1);
1499
1500 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN);
1501 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_DACEN);
1502 }
1503
clk_stm32_pll_get_pdata(unsigned int pll_idx)1504 static struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(unsigned int pll_idx)
1505 {
1506 struct clk_stm32_priv *priv = clk_stm32_get_priv();
1507 struct stm32_clk_platdata *pdata = priv->pdata;
1508
1509 assert(pll_idx < pdata->npll);
1510
1511 return &pdata->pll[pll_idx];
1512 }
1513
clk_stm32_pll_set_mux(struct clk_stm32_priv * priv __unused,uint32_t src)1514 static int clk_stm32_pll_set_mux(struct clk_stm32_priv *priv __unused,
1515 uint32_t src)
1516 {
1517 int mux = (src & MUX_ID_MASK) >> MUX_ID_SHIFT;
1518 int sel = (src & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
1519
1520 if (stm32_mux_set_parent(mux, sel))
1521 return -1;
1522 else
1523 return 0;
1524 }
1525
clk_stm32_pll_check_mux(struct clk_stm32_priv * priv __unused,uint32_t src)1526 static int clk_stm32_pll_check_mux(struct clk_stm32_priv *priv __unused,
1527 uint32_t src)
1528 {
1529 int mux = (src & MUX_ID_MASK) >> MUX_ID_SHIFT;
1530 int sel = (src & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
1531
1532 return stm32_mux_get_parent(mux) != (size_t)sel ? 1 : 0;
1533 }
1534
clk_stm32_pll1_init(struct clk_stm32_priv * priv,int pll_idx __unused,struct stm32_pll_dt_cfg * pll_conf)1535 static void clk_stm32_pll1_init(struct clk_stm32_priv *priv,
1536 int pll_idx __unused,
1537 struct stm32_pll_dt_cfg *pll_conf)
1538 {
1539 int sel = (pll_conf->src & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
1540 unsigned long refclk = 0;
1541 int ret = 0;
1542
1543 stm32mp2_a35_ss_on_bypass();
1544
1545 if (stm32_rcc_has_access_by_id(RCC_RIF_PLL4_TO_8))
1546 ret = clk_stm32_pll_set_mux(priv, pll_conf->src);
1547 else
1548 ret = clk_stm32_pll_check_mux(priv, pll_conf->src);
1549
1550 if (ret)
1551 panic();
1552
1553 refclk = clk_stm32_pll_get_oscillator_rate(sel);
1554
1555 /*
1556 * No need to check max clock, as oscillator reference clocks will
1557 * always be less than 1.2GHz
1558 */
1559 if (refclk < PLL_REFCLK_MIN)
1560 panic();
1561
1562 stm32mp2_a35_pll1_config(pll_conf->cfg[FBDIV],
1563 pll_conf->cfg[REFDIV],
1564 pll_conf->cfg[POSTDIV1],
1565 pll_conf->cfg[POSTDIV2]);
1566
1567 if (stm32mp2_a35_pll1_start())
1568 panic();
1569 }
1570
clk_stm32_pll_init(struct clk_stm32_priv * priv,int pll_idx,struct stm32_pll_dt_cfg * pll_conf)1571 static void clk_stm32_pll_init(struct clk_stm32_priv *priv, int pll_idx,
1572 struct stm32_pll_dt_cfg *pll_conf)
1573 {
1574 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx);
1575 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
1576 bool spread_spectrum = false;
1577
1578 if (stm32_gate_rdy_disable(pll->gate_id))
1579 panic();
1580
1581 if (clk_stm32_pll_set_mux(priv, pll_conf->src))
1582 panic();
1583
1584 clk_stm32_pll_config_output(priv, pll, pll_conf->src,
1585 pll_conf->cfg, pll_conf->frac);
1586
1587 if (pll_conf->csg_enabled) {
1588 clk_stm32_pll_config_csg(priv, pll, pll_conf->csg);
1589 spread_spectrum = true;
1590 }
1591
1592 if (stm32_gate_rdy_enable(pll->gate_id))
1593 panic();
1594
1595 if (spread_spectrum)
1596 io_clrbits32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST);
1597 }
1598
stm32_clk_pll_configure(struct clk_stm32_priv * priv)1599 static int stm32_clk_pll_configure(struct clk_stm32_priv *priv)
1600 {
1601 struct stm32_pll_dt_cfg *pll_conf = NULL;
1602 size_t i = 0;
1603
1604 for (i = 0; i < PLL_NB; i++) {
1605 /* Skip the PLL3 (not present in the STM32MP21 SOC) */
1606 if (i == PLL3_ID)
1607 continue;
1608
1609 pll_conf = clk_stm32_pll_get_pdata(i);
1610
1611 if (pll_conf->enabled) {
1612 /* Skip the PLL2 (reserved to DDR) */
1613 if (i == PLL2_ID)
1614 continue;
1615
1616 if (i == PLL1_ID)
1617 clk_stm32_pll1_init(priv, i, pll_conf);
1618 else
1619 clk_stm32_pll_init(priv, i, pll_conf);
1620 }
1621 }
1622
1623 return 0;
1624 }
1625
1626 #define __WORD_BIT 32
1627
wait_predivsr(uint16_t channel)1628 static int wait_predivsr(uint16_t channel)
1629 {
1630 uintptr_t rcc_base = stm32_rcc_base();
1631 uintptr_t previvsr = 0;
1632 uint32_t channel_bit = 0;
1633 uint32_t value = 0;
1634
1635 if (channel < __WORD_BIT) {
1636 previvsr = rcc_base + RCC_PREDIVSR1;
1637 channel_bit = BIT(channel);
1638 } else {
1639 previvsr = rcc_base + RCC_PREDIVSR2;
1640 channel_bit = BIT(channel - __WORD_BIT);
1641 }
1642
1643 if (IO_READ32_POLL_TIMEOUT(previvsr, value, !(value & channel_bit), 0,
1644 CLKDIV_TIMEOUT)) {
1645 EMSG("Pre divider status: %#"PRIx32, io_read32(previvsr));
1646 return -1;
1647 }
1648
1649 return 0;
1650 }
1651
wait_findivsr(uint16_t channel)1652 static int wait_findivsr(uint16_t channel)
1653 {
1654 uintptr_t rcc_base = stm32_rcc_base();
1655 uintptr_t finvivsr = 0;
1656 uint32_t channel_bit = 0;
1657 uint32_t value = 0;
1658
1659 if (channel < __WORD_BIT) {
1660 finvivsr = rcc_base + RCC_FINDIVSR1;
1661 channel_bit = BIT(channel);
1662 } else {
1663 finvivsr = rcc_base + RCC_FINDIVSR2;
1664 channel_bit = BIT(channel - __WORD_BIT);
1665 }
1666
1667 if (IO_READ32_POLL_TIMEOUT(finvivsr, value, !(value & channel_bit), 0,
1668 CLKDIV_TIMEOUT)) {
1669 EMSG("Final divider status: %#"PRIx32, io_read32(finvivsr));
1670 return -1;
1671 }
1672
1673 return 0;
1674 }
1675
wait_xbar_sts(uint16_t channel)1676 static int wait_xbar_sts(uint16_t channel)
1677 {
1678 uintptr_t rcc_base = stm32_rcc_base();
1679 uintptr_t xbar_cfgr = rcc_base + RCC_XBAR0CFGR + (0x4 * channel);
1680 uint32_t value = 0;
1681
1682 if (IO_READ32_POLL_TIMEOUT(xbar_cfgr, value,
1683 !(value & RCC_XBAR0CFGR_XBAR0STS), 0,
1684 CLKDIV_TIMEOUT)) {
1685 EMSG("XBAR%"PRIu16"CFGR: %#"PRIx32, channel,
1686 io_read32(xbar_cfgr));
1687 return -1;
1688 }
1689
1690 return 0;
1691 }
1692
flexclkgen_search_config(uint16_t channel,unsigned int * clk_src,unsigned int * prediv,unsigned int * findiv)1693 static TEE_Result flexclkgen_search_config(uint16_t channel,
1694 unsigned int *clk_src,
1695 unsigned int *prediv,
1696 unsigned int *findiv)
1697 {
1698 struct clk_stm32_priv *priv = clk_stm32_get_priv();
1699 struct stm32_clk_platdata *pdata = priv->pdata;
1700 unsigned int flex_id = U(0);
1701 uint32_t dt_cfg = U(0);
1702 uint32_t i = U(0);
1703
1704 assert(clk_src && prediv && findiv);
1705
1706 /*
1707 * pdata->flexgen is the array of all the flexgen configuration from
1708 * the device tree.
1709 * The binding does not enforce the description of all flexgen nor
1710 * the order it which they are listed.
1711 */
1712 for (i = 0; i < pdata->nflexgen; i++) {
1713 dt_cfg = pdata->flexgen[i];
1714
1715 flex_id = (dt_cfg & FLEX_ID_MASK) >> FLEX_ID_SHIFT;
1716 if (flex_id == channel) {
1717 *clk_src = (dt_cfg & FLEX_SEL_MASK) >> FLEX_SEL_SHIFT;
1718 *prediv = (dt_cfg & FLEX_PDIV_MASK) >> FLEX_PDIV_SHIFT;
1719 *findiv = (dt_cfg & FLEX_FDIV_MASK) >> FLEX_FDIV_SHIFT;
1720
1721 return TEE_SUCCESS;
1722 }
1723 }
1724
1725 return TEE_ERROR_ITEM_NOT_FOUND;
1726 }
1727
flexclkgen_config_channel(uint16_t channel,unsigned int clk_src,unsigned int prediv,unsigned int findiv)1728 static void flexclkgen_config_channel(uint16_t channel, unsigned int clk_src,
1729 unsigned int prediv, unsigned int findiv)
1730 {
1731 uintptr_t rcc_base = stm32_rcc_base();
1732
1733 if (wait_predivsr(channel))
1734 panic();
1735
1736 io_clrsetbits32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel),
1737 RCC_PREDIV0CFGR_PREDIV0_MASK, prediv);
1738
1739 if (wait_predivsr(channel))
1740 panic();
1741
1742 if (wait_findivsr(channel))
1743 panic();
1744
1745 io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel),
1746 RCC_FINDIV0CFGR_FINDIV0_MASK,
1747 findiv);
1748
1749 if (wait_findivsr(channel))
1750 panic();
1751
1752 if (wait_xbar_sts(channel))
1753 panic();
1754
1755 io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel),
1756 RCC_XBAR0CFGR_XBAR0SEL_MASK,
1757 clk_src);
1758
1759 io_setbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel),
1760 RCC_XBAR0CFGR_XBAR0EN);
1761
1762 if (wait_xbar_sts(channel))
1763 panic();
1764 }
1765
stm32mp2_clk_flexgen_configure(struct clk_stm32_priv * priv)1766 static int stm32mp2_clk_flexgen_configure(struct clk_stm32_priv *priv)
1767 {
1768 struct stm32_clk_platdata *pdata = priv->pdata;
1769 uint32_t i = 0;
1770
1771 for (i = 0; i < pdata->nflexgen; i++) {
1772 uint32_t val = pdata->flexgen[i];
1773 uint32_t cmd = 0;
1774 uint32_t cmd_data = 0;
1775 unsigned int channel = 0;
1776 unsigned int clk_src = 0;
1777 unsigned int pdiv = 0;
1778 unsigned int fdiv = 0;
1779
1780 cmd = (val & CMD_MASK) >> CMD_SHIFT;
1781 cmd_data = val & ~CMD_MASK;
1782
1783 if (cmd != CMD_FLEXGEN)
1784 continue;
1785
1786 channel = (cmd_data & FLEX_ID_MASK) >> FLEX_ID_SHIFT;
1787
1788 /*
1789 * Skip ck_ker_stgen configuration, will be done by
1790 * stgen driver.
1791 */
1792 if (channel == FLEX_STGEN)
1793 continue;
1794
1795 clk_src = (cmd_data & FLEX_SEL_MASK) >> FLEX_SEL_SHIFT;
1796 pdiv = (cmd_data & FLEX_PDIV_MASK) >> FLEX_PDIV_SHIFT;
1797 fdiv = (cmd_data & FLEX_FDIV_MASK) >> FLEX_FDIV_SHIFT;
1798
1799 flexclkgen_config_channel(channel, clk_src, pdiv, fdiv);
1800 }
1801
1802 return 0;
1803 }
1804
stm32_clk_configure_div(struct clk_stm32_priv * priv __unused,uint32_t data)1805 static int stm32_clk_configure_div(struct clk_stm32_priv *priv __unused,
1806 uint32_t data)
1807 {
1808 uint32_t div_id = 0;
1809 uint32_t div_n = 0;
1810
1811 div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT;
1812 div_n = (data & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT;
1813
1814 return stm32_div_set_value(div_id, div_n);
1815 }
1816
stm32_clk_configure_mux(struct clk_stm32_priv * priv __unused,uint32_t data)1817 static int stm32_clk_configure_mux(struct clk_stm32_priv *priv __unused,
1818 uint32_t data)
1819 {
1820 int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT;
1821 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
1822
1823 if (stm32_mux_set_parent(mux, sel))
1824 return -1;
1825 else
1826 return 0;
1827 }
1828
stm32_clk_configure_by_addr_val(struct clk_stm32_priv * priv,uint32_t data)1829 static int stm32_clk_configure_by_addr_val(struct clk_stm32_priv *priv,
1830 uint32_t data)
1831 {
1832 uint32_t addr = data >> CLK_ADDR_SHIFT;
1833 uint32_t val = data & CLK_ADDR_VAL_MASK;
1834
1835 io_setbits32(priv->base + addr, val);
1836
1837 return 0;
1838 }
1839
stm32_clk_configure_obs(struct clk_stm32_priv * priv,uint32_t data)1840 static void stm32_clk_configure_obs(struct clk_stm32_priv *priv,
1841 uint32_t data)
1842 {
1843 uint32_t id = (data & OBS_ID_MASK) >> OBS_ID_SHIFT;
1844 uint32_t status = (data & OBS_STATUS_MASK) >> OBS_STATUS_SHIFT;
1845 uint32_t int_ext = (data & OBS_INTEXT_MASK) >> OBS_INTEXT_SHIFT;
1846 uint32_t div = (data & OBS_DIV_MASK) >> OBS_DIV_SHIFT;
1847 uint32_t inv = (data & OBS_INV_MASK) >> OBS_INV_SHIFT;
1848 uint32_t sel = (data & OBS_SEL_MASK) >> OBS_SEL_SHIFT;
1849 uint32_t reg = 0;
1850 uint32_t val = 0;
1851
1852 if (!id)
1853 reg = RCC_FCALCOBS0CFGR;
1854 else
1855 reg = RCC_FCALCOBS1CFGR;
1856
1857 if (status)
1858 val |= RCC_FCALCOBS0CFGR_CKOBSEN;
1859
1860 if (int_ext == OBS_EXT) {
1861 val |= RCC_FCALCOBS0CFGR_CKOBSEXTSEL;
1862 val |= SHIFT_U32(sel, RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT);
1863 } else {
1864 val |= SHIFT_U32(sel, RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT);
1865 }
1866
1867 if (inv)
1868 val |= RCC_FCALCOBS0CFGR_CKOBSINV;
1869
1870 val |= SHIFT_U32(div, RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT);
1871
1872 io_write32(priv->base + reg, val);
1873 }
1874
stm32_clk_configure(struct clk_stm32_priv * priv,uint32_t val)1875 static int stm32_clk_configure(struct clk_stm32_priv *priv, uint32_t val)
1876 {
1877 uint32_t cmd_data = 0;
1878 uint32_t cmd = 0;
1879 int ret = 0;
1880
1881 if (val & CMD_ADDR_BIT) {
1882 cmd_data = val & ~CMD_ADDR_BIT;
1883
1884 return stm32_clk_configure_by_addr_val(priv, cmd_data);
1885 }
1886
1887 cmd = (val & CMD_MASK) >> CMD_SHIFT;
1888 cmd_data = val & ~CMD_MASK;
1889
1890 switch (cmd) {
1891 case CMD_DIV:
1892 ret = stm32_clk_configure_div(priv, cmd_data);
1893 break;
1894
1895 case CMD_MUX:
1896 ret = stm32_clk_configure_mux(priv, cmd_data);
1897 break;
1898
1899 case CMD_OBS:
1900 stm32_clk_configure_obs(priv, cmd_data);
1901 break;
1902
1903 default:
1904 EMSG("cmd unknown ! : %#"PRIx32, val);
1905 ret = -1;
1906 }
1907
1908 return ret;
1909 }
1910
stm32_clk_bus_configure(struct clk_stm32_priv * priv)1911 static int stm32_clk_bus_configure(struct clk_stm32_priv *priv)
1912 {
1913 struct stm32_clk_platdata *pdata = priv->pdata;
1914 uint32_t i = 0;
1915
1916 for (i = 0; i < pdata->nbusclk; i++) {
1917 int ret = 0;
1918
1919 ret = stm32_clk_configure(priv, pdata->busclk[i]);
1920 if (ret)
1921 return ret;
1922 }
1923
1924 return 0;
1925 }
1926
stm32_clk_kernel_configure(struct clk_stm32_priv * priv)1927 static int stm32_clk_kernel_configure(struct clk_stm32_priv *priv)
1928 {
1929 struct stm32_clk_platdata *pdata = priv->pdata;
1930 uint32_t i = 0;
1931
1932 for (i = 0; i < pdata->nkernelclk; i++) {
1933 int ret = 0;
1934
1935 ret = stm32_clk_configure(priv, pdata->kernelclk[i]);
1936 if (ret)
1937 return ret;
1938 }
1939
1940 return 0;
1941 }
1942
stm32mp2_init_clock_tree(struct clk_stm32_priv * priv,struct stm32_clk_platdata * pdata)1943 static void stm32mp2_init_clock_tree(struct clk_stm32_priv *priv,
1944 struct stm32_clk_platdata *pdata)
1945 {
1946 stm32_clk_oscillators_enable(priv, pdata);
1947
1948 /* Come back to HSI for flexgen */
1949 stm32mp2_clk_xbar_on_hsi(priv);
1950
1951 if (stm32_clk_pll_configure(priv))
1952 panic("Cannot configure plls");
1953
1954 /* Wait LSE ready before to use it */
1955 if (stm32_clk_oscillators_wait_lse_ready(priv, pdata))
1956 panic("Timeout: to enable LSE");
1957
1958 if (stm32mp2_clk_flexgen_configure(priv))
1959 panic("Cannot configure flexgen");
1960
1961 if (stm32_clk_bus_configure(priv))
1962 panic("Cannot config bus clocks");
1963
1964 if (stm32_clk_kernel_configure(priv))
1965 panic("Cannot configure kernel clocks");
1966
1967 /* Configure LSE css after RTC source configuration */
1968 stm32_clk_oscillators_lse_set_css(priv, pdata);
1969 }
1970
clk_stm32_osc_enable(struct clk * clk)1971 static TEE_Result clk_stm32_osc_enable(struct clk *clk)
1972 {
1973 if (stm32_rcc_has_access_by_id(RCC_RIF_OSCILLATORS))
1974 return clk_stm32_gate_ready_ops.enable(clk);
1975
1976 return TEE_SUCCESS;
1977 }
1978
clk_stm32_osc_disable(struct clk * clk)1979 static void clk_stm32_osc_disable(struct clk *clk)
1980 {
1981 if (stm32_rcc_has_access_by_id(RCC_RIF_OSCILLATORS))
1982 clk_stm32_gate_ready_ops.disable(clk);
1983 }
1984
1985 static const struct clk_ops clk_stm32_osc_ops = {
1986 .enable = clk_stm32_osc_enable,
1987 .disable = clk_stm32_osc_disable,
1988 };
1989
1990 static const struct clk_ops clk_stm32_oscillator_msi_ops = {
1991 .enable = clk_stm32_osc_enable,
1992 .disable = clk_stm32_osc_disable,
1993 };
1994
1995 /* Clock with no ops, only used as parent for flexgen selection */
1996 static const struct clk_ops clk_stm32_no_ops = {
1997 };
1998
clk_stm32_osc_ker_enable(struct clk * clk)1999 static TEE_Result clk_stm32_osc_ker_enable(struct clk *clk)
2000 {
2001 if (stm32_rcc_has_access_by_id(RCC_RIF_OSCILLATORS))
2002 return clk_stm32_gate_ops.enable(clk);
2003
2004 return TEE_SUCCESS;
2005 }
2006
clk_stm32_osc_ker_disable(struct clk * clk)2007 static void clk_stm32_osc_ker_disable(struct clk *clk)
2008 {
2009 if (stm32_rcc_has_access_by_id(RCC_RIF_OSCILLATORS))
2010 clk_stm32_gate_ops.disable(clk);
2011 }
2012
2013 static const struct clk_ops clk_stm32_osc_ker_ops = {
2014 .enable = clk_stm32_osc_ker_enable,
2015 .disable = clk_stm32_osc_ker_disable,
2016 };
2017
clk_stm32_hse_div_set_rate(struct clk * clk,unsigned long rate,unsigned long parent_rate)2018 static TEE_Result clk_stm32_hse_div_set_rate(struct clk *clk,
2019 unsigned long rate,
2020 unsigned long parent_rate)
2021 {
2022 if (stm32_rcc_has_access_by_id(RCC_RIF_OSCILLATORS))
2023 return clk_stm32_divider_set_rate(clk, rate, parent_rate);
2024
2025 return TEE_SUCCESS;
2026 }
2027
2028 static const struct clk_ops clk_stm32_hse_div_ops = {
2029 .get_rate = clk_stm32_divider_get_rate,
2030 .set_rate = clk_stm32_hse_div_set_rate,
2031 };
2032
clk_stm32_hsediv2_enable(struct clk * clk)2033 static TEE_Result clk_stm32_hsediv2_enable(struct clk *clk)
2034 {
2035 if (stm32_rcc_has_access_by_id(RCC_RIF_OSCILLATORS))
2036 return clk_stm32_gate_ops.enable(clk);
2037
2038 return TEE_SUCCESS;
2039 }
2040
clk_stm32_hsediv2_disable(struct clk * clk)2041 static void clk_stm32_hsediv2_disable(struct clk *clk)
2042 {
2043 if (stm32_rcc_has_access_by_id(RCC_RIF_OSCILLATORS))
2044 clk_stm32_gate_ops.disable(clk);
2045 }
2046
clk_stm32_hsediv2_get_rate(struct clk * clk __unused,unsigned long prate)2047 static unsigned long clk_stm32_hsediv2_get_rate(struct clk *clk __unused,
2048 unsigned long prate)
2049 {
2050 struct clk_stm32_priv *priv = clk_stm32_get_priv();
2051 uintptr_t addr = priv->base + RCC_OCENSETR;
2052
2053 if (io_read32(addr) & RCC_OCENSETR_HSEDIV2BYP)
2054 return prate;
2055
2056 return prate / 2;
2057 }
2058
2059 static const struct clk_ops clk_hsediv2_ops = {
2060 .enable = clk_stm32_hsediv2_enable,
2061 .disable = clk_stm32_hsediv2_disable,
2062 .get_rate = clk_stm32_hsediv2_get_rate,
2063 };
2064
2065 struct clk_stm32_pll_cfg {
2066 uint32_t pll_offset;
2067 int gate_id;
2068 int mux_id;
2069 };
2070
clk_get_pll1_fvco_rate(unsigned long refclk)2071 static unsigned long clk_get_pll1_fvco_rate(unsigned long refclk)
2072 {
2073 uint32_t reg = stm32mp_syscfg_read(CA35SS_SSC_PLL_FREQ1);
2074 uint32_t fbdiv = 0;
2075 uint32_t refdiv = 0;
2076 unsigned long freq = 0;
2077
2078 fbdiv = (reg & CA35SS_SSC_PLL_FREQ1_FBDIV_MASK) >>
2079 CA35SS_SSC_PLL_FREQ1_FBDIV_SHIFT;
2080
2081 refdiv = (reg & CA35SS_SSC_PLL_FREQ1_REFDIV_MASK) >>
2082 CA35SS_SSC_PLL_FREQ1_REFDIV_SHIFT;
2083
2084 if (!refdiv || MUL_OVERFLOW(refclk, fbdiv, &freq))
2085 panic();
2086
2087 return freq / refdiv;
2088 }
2089
clk_stm32_pll1_get_rate(struct clk * clk __unused,unsigned long prate)2090 static unsigned long clk_stm32_pll1_get_rate(struct clk *clk __unused,
2091 unsigned long prate)
2092 {
2093 uint32_t reg = stm32mp_syscfg_read(CA35SS_SSC_PLL_FREQ2);
2094 unsigned long dfout = 0;
2095 uint32_t postdiv1 = 0;
2096 uint32_t postdiv2 = 0;
2097
2098 postdiv1 = (reg & CA35SS_SSC_PLL_FREQ2_POSTDIV1_MASK) >>
2099 CA35SS_SSC_PLL_FREQ2_POSTDIV1_SHIFT;
2100
2101 postdiv2 = (reg & CA35SS_SSC_PLL_FREQ2_POSTDIV2_MASK) >>
2102 CA35SS_SSC_PLL_FREQ2_POSTDIV2_SHIFT;
2103
2104 if (!postdiv1 || !postdiv2)
2105 dfout = prate;
2106 else
2107 dfout = clk_get_pll1_fvco_rate(prate) / (postdiv1 * postdiv2);
2108
2109 return dfout;
2110 }
2111
2112 static struct stm32_clk_opp_cfg *
clk_stm32_get_opp_config(struct stm32_clk_opp_cfg * opp_cfg,unsigned long rate)2113 clk_stm32_get_opp_config(struct stm32_clk_opp_cfg *opp_cfg, unsigned long rate)
2114 {
2115 unsigned int i = 0;
2116
2117 for (i = 0; i < MAX_OPP && opp_cfg->frq; i++, opp_cfg++)
2118 if (opp_cfg->frq == rate)
2119 return opp_cfg;
2120
2121 return NULL;
2122 }
2123
clk_stm32_pll1_set_rate(struct clk * clk __unused,unsigned long rate,unsigned long parent_rate __unused)2124 static TEE_Result clk_stm32_pll1_set_rate(struct clk *clk __unused,
2125 unsigned long rate,
2126 unsigned long parent_rate __unused)
2127 {
2128 struct clk_stm32_priv *priv = clk_stm32_get_priv();
2129 struct stm32_clk_platdata *pdata = priv->pdata;
2130 struct stm32_pll_dt_cfg *pll_conf = NULL;
2131 struct stm32_clk_opp_cfg *opp = NULL;
2132
2133 opp = clk_stm32_get_opp_config(pdata->opp->cpu1_opp, rate);
2134 if (!opp)
2135 return TEE_ERROR_ITEM_NOT_FOUND;
2136
2137 pll_conf = &opp->pll_cfg;
2138
2139 clk_stm32_pll1_init(priv, PLL1_ID, pll_conf);
2140
2141 return TEE_SUCCESS;
2142 }
2143
clk_stm32_pll_get_parent(struct clk * clk)2144 static size_t clk_stm32_pll_get_parent(struct clk *clk)
2145 {
2146 struct clk_stm32_pll_cfg *cfg = clk->priv;
2147
2148 return stm32_mux_get_parent(cfg->mux_id);
2149 }
2150
2151 static const struct clk_ops clk_stm32_pll1_ops = {
2152 .get_parent = clk_stm32_pll_get_parent,
2153 .get_rate = clk_stm32_pll1_get_rate,
2154 .set_rate = clk_stm32_pll1_set_rate,
2155 };
2156
clk_get_pll_fvco(uint32_t offset_base,unsigned long prate)2157 static unsigned long clk_get_pll_fvco(uint32_t offset_base,
2158 unsigned long prate)
2159 {
2160 struct clk_stm32_priv *priv = clk_stm32_get_priv();
2161 uintptr_t pllxcfgr1 = priv->base + offset_base;
2162 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2;
2163 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;
2164 unsigned long fvco = 0;
2165 uint32_t fracin = 0;
2166 uint32_t fbdiv = 0;
2167 uint32_t refdiv = 0;
2168
2169 fracin = io_read32(pllxcfgr3) & RCC_PLLxCFGR3_FRACIN_MASK;
2170 fbdiv = (io_read32(pllxcfgr2) & RCC_PLLxCFGR2_FBDIV_MASK) >>
2171 RCC_PLLxCFGR2_FBDIV_SHIFT;
2172
2173 refdiv = io_read32(pllxcfgr2) & RCC_PLLxCFGR2_FREFDIV_MASK;
2174
2175 assert(refdiv);
2176
2177 if (fracin) {
2178 unsigned long long numerator = 0;
2179 unsigned long long denominator = 0;
2180
2181 numerator = SHIFT_U64(fbdiv, 24) + fracin;
2182 numerator = prate * numerator;
2183 denominator = SHIFT_U64(refdiv, 24);
2184 fvco = (unsigned long)(numerator / denominator);
2185 } else {
2186 fvco = (unsigned long)(prate * fbdiv / refdiv);
2187 }
2188
2189 return fvco;
2190 }
2191
clk_stm32_pll_get_rate(struct clk * clk __unused,unsigned long prate)2192 static unsigned long clk_stm32_pll_get_rate(struct clk *clk __unused,
2193 unsigned long prate)
2194 {
2195 struct clk_stm32_priv *priv = clk_stm32_get_priv();
2196 struct clk_stm32_pll_cfg *cfg = clk->priv;
2197 uintptr_t pllxcfgr1 = priv->base + cfg->pll_offset;
2198 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;
2199 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6;
2200 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7;
2201 unsigned long dfout = 0;
2202 uint32_t postdiv1 = 0;
2203 uint32_t postdiv2 = 0;
2204
2205 postdiv1 = io_read32(pllxcfgr6) & RCC_PLLxCFGR6_POSTDIV1_MASK;
2206 postdiv2 = io_read32(pllxcfgr7) & RCC_PLLxCFGR7_POSTDIV2_MASK;
2207
2208 if ((io_read32(pllxcfgr4) & RCC_PLLxCFGR4_BYPASS) ||
2209 !postdiv1 || !postdiv2)
2210 dfout = prate;
2211 else
2212 dfout = clk_get_pll_fvco(cfg->pll_offset,
2213 prate) / (postdiv1 * postdiv2);
2214
2215 return dfout;
2216 }
2217
clk_stm32_pll_enable(struct clk * clk)2218 static TEE_Result clk_stm32_pll_enable(struct clk *clk)
2219 {
2220 struct clk_stm32_pll_cfg *cfg = clk->priv;
2221
2222 if (stm32_rcc_has_access_by_id(RCC_RIF_PLL4_TO_8)) {
2223 if (stm32_gate_rdy_enable(cfg->gate_id)) {
2224 EMSG("%s timeout", clk_get_name(clk));
2225 return TEE_ERROR_TIMEOUT;
2226 }
2227 }
2228
2229 return TEE_SUCCESS;
2230 }
2231
clk_stm32_pll_disable(struct clk * clk)2232 static void clk_stm32_pll_disable(struct clk *clk)
2233 {
2234 struct clk_stm32_pll_cfg *cfg = clk->priv;
2235
2236 if (stm32_rcc_has_access_by_id(RCC_RIF_PLL4_TO_8))
2237 if (stm32_gate_rdy_disable(cfg->gate_id) != 0U)
2238 EMSG("%s timeout", clk_get_name(clk));
2239 }
2240
2241 static const struct clk_ops clk_stm32_pll_ops = {
2242 .get_parent = clk_stm32_pll_get_parent,
2243 .get_rate = clk_stm32_pll_get_rate,
2244 .enable = clk_stm32_pll_enable,
2245 .disable = clk_stm32_pll_disable,
2246 };
2247
2248 struct clk_stm32_flexgen_cfg {
2249 int flex_id;
2250 };
2251
clk_stm32_flexgen_get_parent(struct clk * clk)2252 static size_t clk_stm32_flexgen_get_parent(struct clk *clk)
2253 {
2254 struct clk_stm32_flexgen_cfg *cfg = clk->priv;
2255 uintptr_t rcc_base = clk_stm32_get_rcc_base();
2256 uint32_t address = 0;
2257
2258 address = rcc_base + RCC_XBAR0CFGR + (cfg->flex_id * 4);
2259
2260 return io_read32(address) & RCC_XBAR0CFGR_XBAR0SEL_MASK;
2261 }
2262
clk_stm32_flexgen_set_parent(struct clk * clk,size_t pidx)2263 static TEE_Result clk_stm32_flexgen_set_parent(struct clk *clk, size_t pidx)
2264 {
2265 uintptr_t rcc_base = clk_stm32_get_rcc_base();
2266 struct clk_stm32_flexgen_cfg *cfg = clk->priv;
2267 uint16_t channel = cfg->flex_id * 4;
2268
2269 if (stm32_rcc_has_access_by_id(cfg->flex_id)) {
2270 io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (channel),
2271 RCC_XBAR0CFGR_XBAR0SEL_MASK, pidx);
2272
2273 if (wait_xbar_sts(channel))
2274 return TEE_ERROR_GENERIC;
2275 }
2276
2277 return TEE_SUCCESS;
2278 }
2279
clk_stm32_flexgen_get_rate(struct clk * clk,unsigned long prate)2280 static unsigned long clk_stm32_flexgen_get_rate(struct clk *clk,
2281 unsigned long prate)
2282 {
2283 struct clk_stm32_flexgen_cfg *cfg = clk->priv;
2284 uintptr_t rcc_base = clk_stm32_get_rcc_base();
2285 uint32_t prediv = 0;
2286 uint32_t findiv = 0;
2287 uint8_t channel = cfg->flex_id;
2288 unsigned long freq = prate;
2289
2290 prediv = io_read32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel)) &
2291 RCC_PREDIV0CFGR_PREDIV0_MASK;
2292 findiv = io_read32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel)) &
2293 RCC_FINDIV0CFGR_FINDIV0_MASK;
2294
2295 if (!freq)
2296 return 0;
2297
2298 switch (prediv) {
2299 case 0x0:
2300 break;
2301
2302 case 0x1:
2303 freq /= 2;
2304 break;
2305
2306 case 0x3:
2307 freq /= 4;
2308 break;
2309
2310 case 0x3FF:
2311 freq /= 1024;
2312 break;
2313
2314 default:
2315 EMSG("Unsupported PREDIV value (%#"PRIx32")", prediv);
2316 panic();
2317 }
2318
2319 freq /= findiv + 1;
2320
2321 return freq;
2322 }
2323
2324 /* Fexgen findiv (final divisor) max value */
2325 #define FLEXGEN_FINDIV_MAX U(64)
2326
clk_stm32_flexgen_get_round_rate(unsigned long rate,unsigned long prate,unsigned int * prediv,unsigned int * findiv)2327 static unsigned long clk_stm32_flexgen_get_round_rate(unsigned long rate,
2328 unsigned long prate,
2329 unsigned int *prediv,
2330 unsigned int *findiv)
2331 {
2332 unsigned int pre_val[] = { 0x0, 0x1, 0x3, 0x3FF };
2333 unsigned int pre_div[] = { 1, 2, 4, 1024 };
2334 long best_diff = LONG_MAX;
2335 unsigned int i = 0;
2336
2337 *prediv = 0;
2338 *findiv = 0;
2339
2340 for (i = 0; i < ARRAY_SIZE(pre_div); i++) {
2341 unsigned long freq = 0;
2342 unsigned long ratio = 0;
2343 long diff = 0L;
2344
2345 freq = UDIV_ROUND_NEAREST((uint64_t)prate, pre_div[i]);
2346 ratio = UDIV_ROUND_NEAREST((uint64_t)freq, rate);
2347
2348 if (!ratio)
2349 ratio = 1;
2350 else if (ratio > FLEXGEN_FINDIV_MAX)
2351 ratio = FLEXGEN_FINDIV_MAX;
2352
2353 freq = UDIV_ROUND_NEAREST((uint64_t)freq, ratio);
2354 if (freq < rate)
2355 diff = rate - freq;
2356 else
2357 diff = freq - rate;
2358
2359 if (diff < best_diff) {
2360 best_diff = diff;
2361 *prediv = pre_val[i];
2362 *findiv = ratio - 1;
2363
2364 if (!diff)
2365 break;
2366 }
2367 }
2368
2369 return (prate / (*prediv + 1)) / (*findiv + 1);
2370 }
2371
clk_stm32_flexgen_set_rate(struct clk * clk,unsigned long rate,unsigned long parent_rate)2372 static TEE_Result clk_stm32_flexgen_set_rate(struct clk *clk,
2373 unsigned long rate,
2374 unsigned long parent_rate)
2375 {
2376 struct clk_stm32_flexgen_cfg *cfg = clk->priv;
2377 uint8_t channel = cfg->flex_id;
2378 uintptr_t rcc_base = stm32_rcc_base();
2379 unsigned int prediv = 0;
2380 unsigned int findiv = 0;
2381
2382 if (!stm32_rcc_has_access_by_id(cfg->flex_id))
2383 return TEE_SUCCESS;
2384
2385 clk_stm32_flexgen_get_round_rate(rate, parent_rate, &prediv, &findiv);
2386
2387 if (wait_predivsr(channel))
2388 panic();
2389
2390 io_clrsetbits32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel),
2391 RCC_PREDIV0CFGR_PREDIV0_MASK,
2392 prediv);
2393
2394 if (wait_predivsr(channel))
2395 panic();
2396
2397 if (wait_findivsr(channel))
2398 panic();
2399
2400 io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel),
2401 RCC_FINDIV0CFGR_FINDIV0_MASK,
2402 findiv);
2403
2404 if (wait_findivsr(channel))
2405 panic();
2406
2407 return TEE_SUCCESS;
2408 }
2409
clk_stm32_flexgen_enable(struct clk * clk)2410 static TEE_Result clk_stm32_flexgen_enable(struct clk *clk)
2411 {
2412 struct clk_stm32_flexgen_cfg *cfg = clk->priv;
2413 uintptr_t rcc_base = clk_stm32_get_rcc_base();
2414 TEE_Result ret = TEE_ERROR_GENERIC;
2415 uint8_t channel = cfg->flex_id;
2416
2417 if (!stm32_rcc_has_access_by_id(channel))
2418 return TEE_SUCCESS;
2419
2420 /*
2421 * Configure flexgen of STGEN since it has been skipped during
2422 * flexgen configuration.
2423 */
2424 if (channel == FLEX_STGEN) {
2425 unsigned int clk_src = U(0);
2426 unsigned int pdiv = U(0);
2427 unsigned int fdiv = U(0);
2428
2429 ret = flexclkgen_search_config(channel, &clk_src, &pdiv, &fdiv);
2430 if (ret) {
2431 EMSG("Error %#"PRIx32" when getting STGEN flexgen conf",
2432 ret);
2433 return ret;
2434 }
2435
2436 flexclkgen_config_channel(channel, clk_src, pdiv, fdiv);
2437
2438 /* Update parent */
2439 clk->parent = clk_get_parent_by_index(clk, clk_src);
2440 }
2441
2442 io_setbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel),
2443 RCC_FINDIV0CFGR_FINDIV0EN);
2444
2445 return TEE_SUCCESS;
2446 }
2447
clk_stm32_flexgen_disable(struct clk * clk)2448 static void clk_stm32_flexgen_disable(struct clk *clk)
2449 {
2450 struct clk_stm32_flexgen_cfg *cfg = clk->priv;
2451 uintptr_t rcc_base = clk_stm32_get_rcc_base();
2452 uint8_t channel = cfg->flex_id;
2453
2454 if (stm32_rcc_has_access_by_id(cfg->flex_id))
2455 io_clrbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel),
2456 RCC_FINDIV0CFGR_FINDIV0EN);
2457 }
2458
2459 static const struct clk_ops clk_stm32_flexgen_ops = {
2460 .get_rate = clk_stm32_flexgen_get_rate,
2461 .set_rate = clk_stm32_flexgen_set_rate,
2462 .get_parent = clk_stm32_flexgen_get_parent,
2463 .set_parent = clk_stm32_flexgen_set_parent,
2464 .enable = clk_stm32_flexgen_enable,
2465 .disable = clk_stm32_flexgen_disable,
2466 };
2467
clk_cpu1_get_parent(struct clk * clk __unused)2468 static size_t clk_cpu1_get_parent(struct clk *clk __unused)
2469 {
2470 uint32_t reg = stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ);
2471
2472 return (reg & CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK) >>
2473 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_SHIFT;
2474 }
2475
2476 static const struct clk_ops clk_stm32_cpu1_ops = {
2477 .get_parent = clk_cpu1_get_parent,
2478 };
2479
2480 #define APB_DIV_MASK GENMASK_32(2, 0)
2481 #define TIM_PRE_MASK BIT(0)
2482
ck_timer_get_rate_ops(struct clk * clk,unsigned long prate)2483 static unsigned long ck_timer_get_rate_ops(struct clk *clk, unsigned long prate)
2484 {
2485 struct clk_stm32_timer_cfg *cfg = clk->priv;
2486 uintptr_t rcc_base = clk_stm32_get_rcc_base();
2487 uint32_t prescaler = 0;
2488 uint32_t timpre = 0;
2489
2490 prescaler = io_read32(rcc_base + cfg->apbdiv) & APB_DIV_MASK;
2491
2492 timpre = io_read32(rcc_base + cfg->timpre) & TIM_PRE_MASK;
2493
2494 if (!prescaler)
2495 return prate;
2496
2497 return prate * (timpre + 1) * 2;
2498 };
2499
2500 static const struct clk_ops ck_timer_ops = {
2501 .get_rate = ck_timer_get_rate_ops,
2502 };
2503
2504 #define PLL_PARENTS { &ck_hsi, &ck_hse, &ck_msi }
2505 #define PLL_NUM_PATENTS 3
2506
2507 #define STM32_OSC(_name, _flags, _gate_id)\
2508 struct clk _name = {\
2509 .ops = &clk_stm32_osc_ops,\
2510 .priv = &(struct clk_stm32_gate_cfg){\
2511 .gate_id = (_gate_id),\
2512 },\
2513 .name = #_name,\
2514 .flags = (_flags),\
2515 .num_parents = 1,\
2516 .parents = { NULL },\
2517 }
2518
2519 #define STM32_OSC_MSI(_name, _flags, _gate_id)\
2520 struct clk _name = {\
2521 .ops = &clk_stm32_oscillator_msi_ops,\
2522 .priv = &(struct clk_stm32_gate_cfg){\
2523 .gate_id = (_gate_id),\
2524 },\
2525 .name = #_name,\
2526 .flags = (_flags),\
2527 .num_parents = 1,\
2528 .parents = { NULL },\
2529 }
2530
2531 #define STM32_OSC_KER(_name)\
2532 struct clk _name = {\
2533 .ops = &clk_stm32_no_ops,\
2534 .name = #_name,\
2535 .num_parents = 1,\
2536 .parents = { NULL },\
2537 }
2538
2539 #define STM32_OSC_KERON(_name, _parent, _gate_id)\
2540 struct clk _name = {\
2541 .ops = &clk_stm32_osc_ker_ops,\
2542 .priv = &(struct clk_stm32_gate_cfg){\
2543 .gate_id = (_gate_id),\
2544 },\
2545 .name = #_name,\
2546 .num_parents = 1,\
2547 .parents = { (_parent) },\
2548 }
2549
2550 #define STM32_HSE_DIV2(_name, _parent, _flags, _gate_id)\
2551 struct clk _name = {\
2552 .ops = &clk_hsediv2_ops,\
2553 .priv = &(struct clk_stm32_gate_cfg){\
2554 .gate_id = (_gate_id),\
2555 },\
2556 .name = #_name,\
2557 .flags = (_flags),\
2558 .num_parents = 1,\
2559 .parents = { (_parent) },\
2560 }
2561
2562 #define STM32_HSE_RTC(_name, _parent, _flags, _div_id)\
2563 struct clk _name = {\
2564 .ops = &clk_stm32_hse_div_ops,\
2565 .priv = &(struct clk_stm32_div_cfg){\
2566 .div_id = (_div_id),\
2567 },\
2568 .name = #_name,\
2569 .flags = (_flags),\
2570 .num_parents = 1,\
2571 .parents = { (_parent) },\
2572 }
2573
2574 #define STM32_PLL1(_name, _flags, _mux_id)\
2575 struct clk _name = {\
2576 .ops = &clk_stm32_pll1_ops,\
2577 .priv = &(struct clk_stm32_pll_cfg){\
2578 .mux_id = (_mux_id),\
2579 },\
2580 .name = #_name,\
2581 .flags = (_flags),\
2582 .num_parents = PLL_NUM_PATENTS,\
2583 .parents = PLL_PARENTS,\
2584 }
2585
2586 #define STM32_PLL2(_name, _flags, _reg, _gate_id, _mux_id)\
2587 struct clk _name = {\
2588 .ops = &clk_stm32_pll_ops,\
2589 .priv = &(struct clk_stm32_pll_cfg){\
2590 .pll_offset = (_reg),\
2591 .gate_id = (_gate_id),\
2592 .mux_id = (_mux_id),\
2593 },\
2594 .name = #_name,\
2595 .flags = (_flags),\
2596 .num_parents = PLL_NUM_PATENTS,\
2597 .parents = PLL_PARENTS,\
2598 }
2599
2600 #define STM32_PLLS(_name, _flags, _reg, _gate_id, _mux_id)\
2601 struct clk _name = {\
2602 .ops = &clk_stm32_pll_ops,\
2603 .priv = &(struct clk_stm32_pll_cfg){\
2604 .pll_offset = (_reg),\
2605 .gate_id = (_gate_id),\
2606 .mux_id = (_mux_id),\
2607 },\
2608 .name = #_name,\
2609 .flags = (_flags),\
2610 .num_parents = PLL_NUM_PATENTS,\
2611 .parents = PLL_PARENTS,\
2612 }
2613
2614 #define RIF_COMPOSITE(_name, _nb_parents, _parents, _flags,\
2615 _gate_id, _div_id, _mux_id, _sec_id)\
2616 struct clk _name = {\
2617 .ops = &clk_stm32_rif_composite_ops,\
2618 .priv = &(struct clk_stm32_rif_composite_cfg){\
2619 .sec_id = (_sec_id),\
2620 .gate_id = (_gate_id),\
2621 .div_id = (_div_id),\
2622 .mux_id = (_mux_id),\
2623 },\
2624 .name = #_name,\
2625 .flags = (_flags),\
2626 .num_parents = (_nb_parents),\
2627 .parents = _parents,\
2628 }
2629
2630 static STM32_FIXED_RATE(ck_off, RCC_0_MHZ);
2631
2632 static STM32_FIXED_RATE(ck_obser0, 0);
2633 static STM32_FIXED_RATE(ck_obser1, 0);
2634 static STM32_FIXED_RATE(spdifsymb, 0);
2635
2636 /* Oscillator clocks */
2637 static STM32_OSC(ck_hsi, 0, GATE_HSI);
2638 static STM32_OSC(ck_hse, 0, GATE_HSE);
2639 static STM32_OSC_MSI(ck_msi, 0, GATE_MSI);
2640 static STM32_OSC(ck_lsi, 0, GATE_LSI);
2641 static STM32_OSC(ck_lse, 0, GATE_LSE);
2642
2643 /* OSC KER is an alternate source of flexgen (dynamically gated) */
2644 static STM32_OSC_KER(ck_hsi_ker);
2645 static STM32_OSC_KER(ck_hse_ker);
2646 static STM32_OSC_KER(ck_msi_ker);
2647
2648 /* OSC_KERON is OSC KER gated by KERON for low power */
2649 static STM32_OSC_KERON(ck_hsi_keron, &ck_hsi_ker, GATE_HSI_KER);
2650 static STM32_OSC_KERON(ck_hse_keron, &ck_hse_ker, GATE_HSE_KER);
2651 static STM32_OSC_KERON(ck_msi_keron, &ck_msi_ker, GATE_MSI_KER);
2652
2653 static STM32_HSE_DIV2(ck_hse_div2, &ck_hse, 0, GATE_HSEDIV2);
2654 static STM32_HSE_RTC(ck_hse_rtc, &ck_hse, 0, DIV_RTC);
2655
2656 static STM32_FIXED_FACTOR(i2sckin, NULL, 0, 1, 1);
2657
2658 static STM32_PLL1(ck_pll1, 0, MUX_MUXSEL5);
2659 static STM32_PLL2(ck_pll2, 0, RCC_PLL2CFGR1, GATE_PLL2, MUX_MUXSEL6);
2660 static STM32_PLLS(ck_pll4, 0, RCC_PLL4CFGR1, GATE_PLL4, MUX_MUXSEL0);
2661 static STM32_PLLS(ck_pll5, 0, RCC_PLL5CFGR1, GATE_PLL5, MUX_MUXSEL1);
2662 static STM32_PLLS(ck_pll6, 0, RCC_PLL6CFGR1, GATE_PLL6, MUX_MUXSEL2);
2663 static STM32_PLLS(ck_pll7, 0, RCC_PLL7CFGR1, GATE_PLL7, MUX_MUXSEL3);
2664 static STM32_PLLS(ck_pll8, 0, RCC_PLL8CFGR1, GATE_PLL8, MUX_MUXSEL4);
2665
2666 #define STM32_FLEXGEN(_name, _flags, _flex_id)\
2667 struct clk _name = {\
2668 .ops = &clk_stm32_flexgen_ops,\
2669 .priv = &(struct clk_stm32_flexgen_cfg){\
2670 .flex_id = (_flex_id),\
2671 },\
2672 .name = #_name,\
2673 .flags = (_flags) | CLK_SET_RATE_UNGATE,\
2674 .num_parents = 15,\
2675 .parents = {\
2676 &ck_pll4, &ck_pll5, &ck_pll6, &ck_pll7, &ck_pll8,\
2677 &ck_hsi, &ck_hse, &ck_msi,\
2678 &ck_hsi_ker, &ck_hse_ker, &ck_msi_ker,\
2679 &spdifsymb, &i2sckin, &ck_lsi, &ck_lse\
2680 },\
2681 }
2682
2683 static STM32_FLEXGEN(ck_icn_hs_mcu, 0, 0);
2684 static STM32_FLEXGEN(ck_icn_sdmmc, 0, 1);
2685 static STM32_FLEXGEN(ck_icn_ddr, 0, 2);
2686 static STM32_FLEXGEN(ck_icn_display, 0, 3);
2687 static STM32_FLEXGEN(ck_icn_hsl, 0, 4);
2688 static STM32_FLEXGEN(ck_icn_nic, 0, 5);
2689
2690 static STM32_DIVIDER(ck_icn_ls_mcu, &ck_icn_hs_mcu, 0, DIV_LSMCU);
2691
2692 static STM32_FLEXGEN(ck_flexgen_07, 0, 7);
2693 static STM32_FLEXGEN(ck_flexgen_08, 0, 8);
2694 static STM32_FLEXGEN(ck_flexgen_09, 0, 9);
2695 static STM32_FLEXGEN(ck_flexgen_10, 0, 10);
2696 static STM32_FLEXGEN(ck_flexgen_11, 0, 11);
2697 static STM32_FLEXGEN(ck_flexgen_12, 0, 12);
2698 static STM32_FLEXGEN(ck_flexgen_13, 0, 13);
2699 static STM32_FLEXGEN(ck_flexgen_14, 0, 14);
2700 static STM32_FLEXGEN(ck_flexgen_15, 0, 15);
2701 static STM32_FLEXGEN(ck_flexgen_16, 0, 16);
2702 static STM32_FLEXGEN(ck_flexgen_17, 0, 17);
2703 static STM32_FLEXGEN(ck_flexgen_18, 0, 18);
2704 static STM32_FLEXGEN(ck_flexgen_19, 0, 19);
2705 static STM32_FLEXGEN(ck_flexgen_20, 0, 20);
2706 static STM32_FLEXGEN(ck_flexgen_21, 0, 21);
2707 static STM32_FLEXGEN(ck_flexgen_22, 0, 22);
2708 static STM32_FLEXGEN(ck_flexgen_23, 0, 23);
2709 static STM32_FLEXGEN(ck_flexgen_24, 0, 24);
2710 static STM32_FLEXGEN(ck_flexgen_25, 0, 25);
2711 static STM32_FLEXGEN(ck_flexgen_26, 0, 26);
2712 static STM32_FLEXGEN(ck_flexgen_27, 0, 27);
2713 static STM32_FLEXGEN(ck_flexgen_28, 0, 28);
2714 static STM32_FLEXGEN(ck_flexgen_29, 0, 29);
2715 static STM32_FLEXGEN(ck_flexgen_30, 0, 30);
2716 static STM32_FLEXGEN(ck_flexgen_31, 0, 31);
2717 static STM32_FLEXGEN(ck_flexgen_32, 0, 32);
2718 static STM32_FLEXGEN(ck_flexgen_33, 0, 33);
2719 static STM32_FLEXGEN(ck_flexgen_34, 0, 34);
2720 static STM32_FLEXGEN(ck_flexgen_35, 0, 35);
2721 static STM32_FLEXGEN(ck_flexgen_36, 0, 36);
2722 static STM32_FLEXGEN(ck_flexgen_37, 0, 37);
2723 static STM32_FLEXGEN(ck_flexgen_38, 0, 38);
2724 static STM32_FLEXGEN(ck_flexgen_39, 0, 39);
2725 static STM32_FLEXGEN(ck_flexgen_40, 0, 40);
2726 static STM32_FLEXGEN(ck_flexgen_41, 0, 41);
2727 static STM32_FLEXGEN(ck_flexgen_42, 0, 42);
2728 static STM32_FLEXGEN(ck_flexgen_43, 0, 43);
2729 static STM32_FLEXGEN(ck_flexgen_44, 0, 44);
2730 static STM32_FLEXGEN(ck_flexgen_45, 0, 45);
2731 static STM32_FLEXGEN(ck_flexgen_46, 0, 46);
2732 static STM32_FLEXGEN(ck_flexgen_47, 0, 47);
2733 static STM32_FLEXGEN(ck_flexgen_48, 0, 48);
2734 static STM32_FLEXGEN(ck_flexgen_49, 0, 49);
2735 static STM32_FLEXGEN(ck_flexgen_50, 0, 50);
2736 static STM32_FLEXGEN(ck_flexgen_51, 0, 51);
2737 static STM32_FLEXGEN(ck_flexgen_52, 0, 52);
2738 static STM32_FLEXGEN(ck_flexgen_53, 0, 53);
2739 static STM32_FLEXGEN(ck_flexgen_54, 0, 54);
2740 static STM32_FLEXGEN(ck_flexgen_55, 0, 55);
2741 static STM32_FLEXGEN(ck_flexgen_56, 0, 56);
2742 static STM32_FLEXGEN(ck_flexgen_57, 0, 57);
2743 static STM32_FLEXGEN(ck_flexgen_58, 0, 58);
2744 static STM32_FLEXGEN(ck_flexgen_59, 0, 59);
2745 static STM32_FLEXGEN(ck_flexgen_60, 0, 60);
2746 static STM32_FLEXGEN(ck_flexgen_61, 0, 61);
2747 static STM32_FLEXGEN(ck_flexgen_62, 0, 62);
2748 static STM32_FLEXGEN(ck_flexgen_63, 0, 63);
2749
2750 static struct clk ck_cpu1 = {
2751 .ops = &clk_stm32_cpu1_ops,
2752 .name = "ck_cpu1",
2753 .num_parents = 2,
2754 .parents = { &ck_pll1, &ck_flexgen_63 },
2755 };
2756
2757 static STM32_DIVIDER(ck_icn_apb1, &ck_icn_ls_mcu, 0, DIV_APB1);
2758 static STM32_DIVIDER(ck_icn_apb2, &ck_icn_ls_mcu, 0, DIV_APB2);
2759 static STM32_DIVIDER(ck_icn_apb3, &ck_icn_ls_mcu, 0, DIV_APB3);
2760 static STM32_DIVIDER(ck_icn_apb4, &ck_icn_ls_mcu, 0, DIV_APB4);
2761 static STM32_DIVIDER(ck_icn_apb5, &ck_icn_ls_mcu, 0, DIV_APB5);
2762 static STM32_COMPOSITE(ck_icn_apbdbg, 1, { &ck_icn_ls_mcu }, 0,
2763 GATE_DBG, DIV_APBDBG, NO_MUX);
2764
2765 #define STM32_TIMER(_name, _parent, _flags, _apbdiv, _timpre)\
2766 struct clk _name = {\
2767 .ops = &ck_timer_ops,\
2768 .priv = &(struct clk_stm32_timer_cfg){\
2769 .apbdiv = (_apbdiv),\
2770 .timpre = (_timpre),\
2771 },\
2772 .name = #_name,\
2773 .flags = (_flags),\
2774 .num_parents = 1,\
2775 .parents = { _parent },\
2776 }
2777
2778 /* Kernel Timers */
2779 static STM32_TIMER(ck_timg1, &ck_icn_apb1, 0, RCC_APB1DIVR, RCC_TIMG1PRER);
2780 static STM32_TIMER(ck_timg2, &ck_icn_apb2, 0, RCC_APB2DIVR, RCC_TIMG2PRER);
2781
2782 /* Clocks under RCC RIF protection */
2783 static STM32_GATE(ck_icn_p_dbgmcu, &ck_icn_apb3, 0, GATE_DBGMCU);
2784 static STM32_GATE(ck_dap, &ck_hsi, 0, GATE_DBGMCU);
2785 static STM32_GATE(ck_sys_dbg, &ck_icn_apbdbg, 0, GATE_DBG);
2786 static STM32_GATE(ck_icn_p_stm, &ck_icn_apbdbg, 0, GATE_STM);
2787 static STM32_GATE(ck_icn_s_stm, &ck_icn_ls_mcu, 0, GATE_STM);
2788 static STM32_GATE(ck_ker_tsdbg, &ck_flexgen_43, 0, GATE_DBG);
2789 static STM32_GATE(ck_ker_tpiu, &ck_flexgen_44, 0, GATE_TRACE);
2790 static STM32_GATE(ck_icn_p_etr, &ck_icn_apbdbg, 0, GATE_ETR);
2791 static STM32_GATE(ck_icn_m_etr, &ck_flexgen_45, 0, GATE_ETR);
2792 static STM32_GATE(ck_sys_atb, &ck_flexgen_45, 0, GATE_DBG);
2793 static STM32_GATE(ck_icn_s_sysram, &ck_icn_hs_mcu, 0, GATE_SYSRAM);
2794 static STM32_GATE(ck_icn_s_retram, &ck_icn_hs_mcu, 0, GATE_RETRAM);
2795 static STM32_GATE(ck_icn_s_bkpsram, &ck_icn_ls_mcu, 0, GATE_BKPSRAM);
2796 static STM32_GATE(ck_icn_s_sram1, &ck_icn_hs_mcu, 0, GATE_SRAM1);
2797 static STM32_GATE(ck_icn_p_hpdma1, &ck_icn_ls_mcu, 0, GATE_HPDMA1);
2798 static STM32_GATE(ck_icn_p_hpdma2, &ck_icn_ls_mcu, 0, GATE_HPDMA2);
2799 static STM32_GATE(ck_icn_p_hpdma3, &ck_icn_ls_mcu, 0, GATE_HPDMA3);
2800 static STM32_GATE(ck_icn_p_ipcc1, &ck_icn_ls_mcu, 0, GATE_IPCC1);
2801 static STM32_GATE(ck_icn_p_gpioa, &ck_icn_ls_mcu, 0, GATE_GPIOA);
2802 static STM32_GATE(ck_icn_p_gpiob, &ck_icn_ls_mcu, 0, GATE_GPIOB);
2803 static STM32_GATE(ck_icn_p_gpioc, &ck_icn_ls_mcu, 0, GATE_GPIOC);
2804 static STM32_GATE(ck_icn_p_gpiod, &ck_icn_ls_mcu, 0, GATE_GPIOD);
2805 static STM32_GATE(ck_icn_p_gpioe, &ck_icn_ls_mcu, 0, GATE_GPIOE);
2806 static STM32_GATE(ck_icn_p_gpiof, &ck_icn_ls_mcu, 0, GATE_GPIOF);
2807 static STM32_GATE(ck_icn_p_gpiog, &ck_icn_ls_mcu, 0, GATE_GPIOG);
2808 static STM32_GATE(ck_icn_p_gpioh, &ck_icn_ls_mcu, 0, GATE_GPIOH);
2809 static STM32_GATE(ck_icn_p_gpioi, &ck_icn_ls_mcu, 0, GATE_GPIOI);
2810 static STM32_GATE(ck_icn_p_gpioz, &ck_icn_ls_mcu, 0, GATE_GPIOZ);
2811 static STM32_GATE(ck_icn_p_rtc, &ck_icn_apb5, 0, GATE_RTC);
2812 static STM32_COMPOSITE(ck_rtc, 4,
2813 PARENT(&ck_off, &ck_lse, &ck_lsi, &ck_hse_rtc),
2814 0, GATE_RTCCK, NO_DIV, MUX_RTC);
2815 static STM32_GATE(ck_icn_p_bsec, &ck_icn_apb3, 0, GATE_BSEC);
2816 static STM32_GATE(ck_icn_p_ddrphyc, &ck_icn_ls_mcu, 0, GATE_DDRPHYCAPB);
2817 static STM32_GATE(ck_icn_p_risaf4, &ck_icn_ls_mcu, 0, GATE_DDRCP);
2818 static STM32_GATE(ck_icn_s_ddr, &ck_icn_ddr, 0, GATE_DDRCP);
2819 static STM32_GATE(ck_icn_p_ddrc, &ck_icn_apb4, 0, GATE_DDRCAPB);
2820 static STM32_GATE(ck_icn_p_ddrcfg, &ck_icn_apb4, 0, GATE_DDRCFG);
2821 static STM32_GATE(ck_icn_p_syscpu1, &ck_icn_ls_mcu, 0, GATE_SYSCPU1);
2822 static STM32_COMPOSITE(ck_mco1, 2, PARENT(&ck_flexgen_61, &ck_obser0), 0,
2823 GATE_MCO1, NO_DIV, MUX_MCO1);
2824 static STM32_COMPOSITE(ck_mco2, 2, PARENT(&ck_flexgen_62, &ck_obser1), 0,
2825 GATE_MCO2, NO_DIV, MUX_MCO2);
2826 static STM32_GATE(ck_icn_s_ospi1, &ck_icn_hs_mcu, 0, GATE_OSPI1);
2827 static STM32_GATE(ck_ker_ospi1, &ck_flexgen_48, 0, GATE_OSPI1);
2828 static STM32_GATE(ck_icn_p_fmc, &ck_icn_ls_mcu, 0, GATE_FMC);
2829 static STM32_GATE(ck_ker_fmc, &ck_flexgen_50, 0, GATE_FMC);
2830
2831 /* Kernel Clocks */
2832 static STM32_GATE(ck_icn_p_dcmipssi, &ck_icn_ls_mcu, 0, GATE_DCMIPSSI);
2833 static STM32_GATE(ck_icn_p_crc, &ck_icn_ls_mcu, 0, GATE_CRC);
2834 static STM32_GATE(ck_icn_p_hash1, &ck_icn_ls_mcu, 0, GATE_HASH1);
2835 static STM32_GATE(ck_icn_p_hash2, &ck_icn_ls_mcu, 0, GATE_HASH2);
2836 static STM32_GATE(ck_icn_p_rng1, &ck_icn_ls_mcu, 0, GATE_RNG1);
2837 static STM32_GATE(ck_icn_p_rng2, &ck_icn_ls_mcu, 0, GATE_RNG2);
2838 static STM32_GATE(ck_icn_p_cryp1, &ck_icn_ls_mcu, 0, GATE_CRYP1);
2839 static STM32_GATE(ck_icn_p_cryp2, &ck_icn_ls_mcu, 0, GATE_CRYP2);
2840 static STM32_GATE(ck_icn_p_saes, &ck_icn_ls_mcu, 0, GATE_SAES);
2841 static STM32_GATE(ck_icn_p_pka, &ck_icn_ls_mcu, 0, GATE_PKA);
2842 static STM32_GATE(ck_icn_p_eth1, &ck_icn_ls_mcu, 0, GATE_ETH1);
2843 static STM32_GATE(ck_icn_p_eth2, &ck_icn_ls_mcu, 0, GATE_ETH2);
2844 static STM32_GATE(ck_icn_p_adc1, &ck_icn_ls_mcu, 0, GATE_ADC1);
2845 static STM32_GATE(ck_icn_p_adc2, &ck_icn_ls_mcu, 0, GATE_ADC2);
2846 static STM32_GATE(ck_icn_p_mdf1, &ck_icn_ls_mcu, 0, GATE_MDF1);
2847
2848 static STM32_GATE(ck_icn_m_sdmmc1, &ck_icn_sdmmc, 0, GATE_SDMMC1);
2849 static STM32_GATE(ck_icn_m_sdmmc2, &ck_icn_sdmmc, 0, GATE_SDMMC2);
2850 static STM32_GATE(ck_icn_m_sdmmc3, &ck_icn_sdmmc, 0, GATE_SDMMC3);
2851 static STM32_GATE(ck_icn_m_usbhohci, &ck_icn_hsl, 0, GATE_USBH);
2852 static STM32_GATE(ck_icn_m_usbhehci, &ck_icn_hsl, 0, GATE_USBH);
2853 static STM32_GATE(ck_icn_m_otg, &ck_icn_hsl, 0, GATE_OTG);
2854
2855 static STM32_GATE(ck_icn_p_tim2, &ck_icn_apb1, 0, GATE_TIM2);
2856 static STM32_GATE(ck_icn_p_tim3, &ck_icn_apb1, 0, GATE_TIM3);
2857 static STM32_GATE(ck_icn_p_tim4, &ck_icn_apb1, 0, GATE_TIM4);
2858 static STM32_GATE(ck_icn_p_tim5, &ck_icn_apb1, 0, GATE_TIM5);
2859 static STM32_GATE(ck_icn_p_tim6, &ck_icn_apb1, 0, GATE_TIM6);
2860 static STM32_GATE(ck_icn_p_tim7, &ck_icn_apb1, 0, GATE_TIM7);
2861 static STM32_GATE(ck_icn_p_tim10, &ck_icn_apb1, 0, GATE_TIM10);
2862 static STM32_GATE(ck_icn_p_tim11, &ck_icn_apb1, 0, GATE_TIM11);
2863 static STM32_GATE(ck_icn_p_tim12, &ck_icn_apb1, 0, GATE_TIM12);
2864 static STM32_GATE(ck_icn_p_tim13, &ck_icn_apb1, 0, GATE_TIM13);
2865 static STM32_GATE(ck_icn_p_tim14, &ck_icn_apb1, 0, GATE_TIM14);
2866 static STM32_GATE(ck_icn_p_lptim1, &ck_icn_apb1, 0, GATE_LPTIM1);
2867 static STM32_GATE(ck_icn_p_lptim2, &ck_icn_apb1, 0, GATE_LPTIM2);
2868 static STM32_GATE(ck_icn_p_spi2, &ck_icn_apb1, 0, GATE_SPI2);
2869 static STM32_GATE(ck_icn_p_spi3, &ck_icn_apb1, 0, GATE_SPI3);
2870 static STM32_GATE(ck_icn_p_spdifrx, &ck_icn_apb1, 0, GATE_SPDIFRX);
2871 static STM32_GATE(ck_icn_p_usart2, &ck_icn_apb1, 0, GATE_USART2);
2872 static STM32_GATE(ck_icn_p_usart3, &ck_icn_apb1, 0, GATE_USART3);
2873 static STM32_GATE(ck_icn_p_uart4, &ck_icn_apb1, 0, GATE_UART4);
2874 static STM32_GATE(ck_icn_p_uart5, &ck_icn_apb1, 0, GATE_UART5);
2875 static STM32_GATE(ck_icn_p_i2c1, &ck_icn_apb1, 0, GATE_I2C1);
2876 static STM32_GATE(ck_icn_p_i2c2, &ck_icn_apb1, 0, GATE_I2C2);
2877 static STM32_GATE(ck_icn_p_i3c1, &ck_icn_apb1, 0, GATE_I3C1);
2878 static STM32_GATE(ck_icn_p_i3c2, &ck_icn_apb1, 0, GATE_I3C2);
2879
2880 static STM32_GATE(ck_icn_p_tim1, &ck_icn_apb2, 0, GATE_TIM1);
2881 static STM32_GATE(ck_icn_p_tim8, &ck_icn_apb2, 0, GATE_TIM8);
2882 static STM32_GATE(ck_icn_p_tim15, &ck_icn_apb2, 0, GATE_TIM15);
2883 static STM32_GATE(ck_icn_p_tim16, &ck_icn_apb2, 0, GATE_TIM16);
2884 static STM32_GATE(ck_icn_p_tim17, &ck_icn_apb2, 0, GATE_TIM17);
2885 static STM32_GATE(ck_icn_p_sai1, &ck_icn_apb2, 0, GATE_SAI1);
2886 static STM32_GATE(ck_icn_p_sai2, &ck_icn_apb2, 0, GATE_SAI2);
2887 static STM32_GATE(ck_icn_p_sai3, &ck_icn_apb2, 0, GATE_SAI3);
2888 static STM32_GATE(ck_icn_p_sai4, &ck_icn_apb2, 0, GATE_SAI4);
2889 static STM32_GATE(ck_icn_p_usart1, &ck_icn_apb2, 0, GATE_USART1);
2890 static STM32_GATE(ck_icn_p_usart6, &ck_icn_apb2, 0, GATE_USART6);
2891 static STM32_GATE(ck_icn_p_uart7, &ck_icn_apb2, 0, GATE_UART7);
2892 static STM32_GATE(ck_icn_p_fdcan, &ck_icn_apb2, 0, GATE_FDCAN);
2893 static STM32_GATE(ck_icn_p_spi1, &ck_icn_apb2, 0, GATE_SPI1);
2894 static STM32_GATE(ck_icn_p_spi4, &ck_icn_apb2, 0, GATE_SPI4);
2895 static STM32_GATE(ck_icn_p_spi5, &ck_icn_apb2, 0, GATE_SPI5);
2896
2897 static STM32_GATE(ck_icn_p_iwdg1, &ck_icn_apb3, 0, GATE_IWDG1);
2898 static STM32_GATE(ck_icn_p_iwdg2, &ck_icn_apb3, 0, GATE_IWDG2);
2899 static STM32_GATE(ck_icn_p_iwdg3, &ck_icn_apb3, 0, GATE_IWDG3);
2900 static STM32_GATE(ck_icn_p_iwdg4, &ck_icn_apb3, 0, GATE_IWDG4);
2901 static STM32_GATE(ck_icn_p_wwdg1, &ck_icn_apb3, 0, GATE_WWDG1);
2902 static STM32_GATE(ck_icn_p_vref, &ck_icn_apb3, 0, GATE_VREF);
2903 static STM32_GATE(ck_icn_p_dts, &ck_icn_apb3, 0, GATE_DTS);
2904 static STM32_GATE(ck_icn_p_serc, &ck_icn_apb3, 0, GATE_SERC);
2905 static STM32_GATE(ck_icn_p_hdp, &ck_icn_apb3, 0, GATE_HDP);
2906
2907 static STM32_GATE(ck_icn_p_ltdc, &ck_icn_apb4, 0, GATE_LTDC);
2908 static STM32_GATE(ck_icn_p_csi, &ck_icn_apb4, 0, GATE_CSI);
2909 static STM32_GATE(ck_icn_p_dcmipp, &ck_icn_apb4, 0, GATE_DCMIPP);
2910 static STM32_GATE(ck_icn_p_ddrperfm, &ck_icn_apb4, 0, GATE_DDRPERFM);
2911 static STM32_GATE(ck_icn_p_stgen, &ck_icn_apb4, 0, GATE_STGEN);
2912
2913 static STM32_GATE(ck_icn_p_spi6, &ck_icn_apb5, 0, GATE_SPI6);
2914 static STM32_GATE(ck_icn_p_lpuart1, &ck_icn_apb5, 0, GATE_LPUART1);
2915 static STM32_GATE(ck_icn_p_i2c3, &ck_icn_apb5, 0, GATE_I2C3);
2916 static STM32_GATE(ck_icn_p_lptim3, &ck_icn_apb5, 0, GATE_LPTIM3);
2917 static STM32_GATE(ck_icn_p_lptim4, &ck_icn_apb5, 0, GATE_LPTIM4);
2918 static STM32_GATE(ck_icn_p_lptim5, &ck_icn_apb5, 0, GATE_LPTIM5);
2919 static STM32_GATE(ck_icn_p_i3c3, &ck_icn_apb5, 0, GATE_I3C3);
2920
2921 static STM32_GATE(ck_ker_tim2, &ck_timg1, 0, GATE_TIM2);
2922 static STM32_GATE(ck_ker_tim3, &ck_timg1, 0, GATE_TIM3);
2923 static STM32_GATE(ck_ker_tim4, &ck_timg1, 0, GATE_TIM4);
2924 static STM32_GATE(ck_ker_tim5, &ck_timg1, 0, GATE_TIM5);
2925 static STM32_GATE(ck_ker_tim6, &ck_timg1, 0, GATE_TIM6);
2926 static STM32_GATE(ck_ker_tim7, &ck_timg1, 0, GATE_TIM7);
2927 static STM32_GATE(ck_ker_tim10, &ck_timg1, 0, GATE_TIM10);
2928 static STM32_GATE(ck_ker_tim11, &ck_timg1, 0, GATE_TIM11);
2929 static STM32_GATE(ck_ker_tim12, &ck_timg1, 0, GATE_TIM12);
2930 static STM32_GATE(ck_ker_tim13, &ck_timg1, 0, GATE_TIM13);
2931 static STM32_GATE(ck_ker_tim14, &ck_timg1, 0, GATE_TIM14);
2932 static STM32_GATE(ck_ker_tim1, &ck_timg2, 0, GATE_TIM1);
2933 static STM32_GATE(ck_ker_tim8, &ck_timg2, 0, GATE_TIM8);
2934 static STM32_GATE(ck_ker_tim15, &ck_timg2, 0, GATE_TIM15);
2935 static STM32_GATE(ck_ker_tim16, &ck_timg2, 0, GATE_TIM16);
2936 static STM32_GATE(ck_ker_tim17, &ck_timg2, 0, GATE_TIM17);
2937 static STM32_GATE(ck_ker_lptim1, &ck_flexgen_07, 0, GATE_LPTIM1);
2938 static STM32_GATE(ck_ker_lptim2, &ck_flexgen_07, 0, GATE_LPTIM2);
2939 static STM32_GATE(ck_ker_usart2, &ck_flexgen_08, 0, GATE_USART2);
2940 static STM32_GATE(ck_ker_uart4, &ck_flexgen_08, 0, GATE_UART4);
2941 static STM32_GATE(ck_ker_usart3, &ck_flexgen_09, 0, GATE_USART3);
2942 static STM32_GATE(ck_ker_uart5, &ck_flexgen_09, 0, GATE_UART5);
2943 static STM32_GATE(ck_ker_spi2, &ck_flexgen_10, 0, GATE_SPI2);
2944 static STM32_GATE(ck_ker_spi3, &ck_flexgen_11, 0, GATE_SPI3);
2945 static STM32_GATE(ck_ker_spdifrx, &ck_flexgen_12, 0, GATE_SPDIFRX);
2946 static STM32_GATE(ck_ker_i2c1, &ck_flexgen_13, 0, GATE_I2C1);
2947 static STM32_GATE(ck_ker_i2c2, &ck_flexgen_13, 0, GATE_I2C2);
2948 static STM32_GATE(ck_ker_i3c1, &ck_flexgen_14, 0, GATE_I3C1);
2949 static STM32_GATE(ck_ker_i3c2, &ck_flexgen_14, 0, GATE_I3C2);
2950 static STM32_GATE(ck_ker_spi1, &ck_flexgen_16, 0, GATE_SPI1);
2951 static STM32_GATE(ck_ker_spi4, &ck_flexgen_17, 0, GATE_SPI4);
2952 static STM32_GATE(ck_ker_spi5, &ck_flexgen_17, 0, GATE_SPI5);
2953 static STM32_GATE(ck_ker_usart1, &ck_flexgen_18, 0, GATE_USART1);
2954 static STM32_GATE(ck_ker_usart6, &ck_flexgen_19, 0, GATE_USART6);
2955 static STM32_GATE(ck_ker_uart7, &ck_flexgen_20, 0, GATE_UART7);
2956 static STM32_GATE(ck_ker_mdf1, &ck_flexgen_21, 0, GATE_MDF1);
2957 static STM32_GATE(ck_ker_sai1, &ck_flexgen_22, 0, GATE_SAI1);
2958 static STM32_GATE(ck_ker_sai2, &ck_flexgen_23, 0, GATE_SAI2);
2959 static STM32_GATE(ck_ker_sai3, &ck_flexgen_24, 0, GATE_SAI3);
2960 static STM32_GATE(ck_ker_sai4, &ck_flexgen_25, 0, GATE_SAI4);
2961 static STM32_GATE(ck_ker_fdcan, &ck_flexgen_26, 0, GATE_FDCAN);
2962 static STM32_GATE(ck_ker_csi, &ck_flexgen_29, 0, GATE_CSI);
2963 static STM32_GATE(ck_ker_csitxesc, &ck_flexgen_30, 0, GATE_CSI);
2964 static STM32_GATE(ck_ker_csiphy, &ck_flexgen_31, 0, GATE_CSI);
2965 static STM32_GATE(ck_ker_stgen, &ck_flexgen_33, CLK_SET_RATE_PARENT,
2966 GATE_STGEN);
2967 static STM32_GATE(ck_ker_i3c3, &ck_flexgen_36, 0, GATE_I3C3);
2968 static STM32_GATE(ck_ker_spi6, &ck_flexgen_37, 0, GATE_SPI6);
2969 static STM32_GATE(ck_ker_i2c3, &ck_flexgen_38, 0, GATE_I2C3);
2970 static STM32_GATE(ck_ker_lpuart1, &ck_flexgen_39, 0, GATE_LPUART1);
2971 static STM32_GATE(ck_ker_lptim3, &ck_flexgen_40, 0, GATE_LPTIM3);
2972 static STM32_GATE(ck_ker_lptim4, &ck_flexgen_41, 0, GATE_LPTIM4);
2973 static STM32_GATE(ck_ker_lptim5, &ck_flexgen_42, 0, GATE_LPTIM5);
2974 static STM32_GATE(ck_ker_sdmmc1, &ck_flexgen_51, 0, GATE_SDMMC1);
2975 static STM32_GATE(ck_ker_sdmmc2, &ck_flexgen_52, 0, GATE_SDMMC2);
2976 static STM32_GATE(ck_ker_sdmmc3, &ck_flexgen_53, 0, GATE_SDMMC3);
2977 static STM32_GATE(ck_ker_eth1, &ck_flexgen_54, 0, GATE_ETH1);
2978 static STM32_GATE(ck_ker_eth2, &ck_flexgen_55, 0, GATE_ETH2);
2979 static STM32_GATE(ck_ker_eth1ptp, &ck_flexgen_56, 0, GATE_ETH1);
2980 static STM32_GATE(ck_ker_eth2ptp, &ck_flexgen_56, 0, GATE_ETH2);
2981
2982 static STM32_GATE(ck_ker_eth1stp, &ck_icn_ls_mcu, 0, GATE_ETH1STP);
2983 static STM32_GATE(ck_ker_eth2stp, &ck_icn_ls_mcu, 0, GATE_ETH2STP);
2984
2985 static STM32_GATE(ck_ker_ltdc, &ck_flexgen_27, CLK_SET_RATE_PARENT,
2986 GATE_LTDC);
2987
2988 static STM32_COMPOSITE(ck_ker_adc1, 2, PARENT(&ck_flexgen_46, &ck_icn_ls_mcu),
2989 0, GATE_ADC1, NO_DIV, MUX_ADC1);
2990
2991 static STM32_COMPOSITE(ck_ker_adc2, 3, PARENT(&ck_flexgen_47, &ck_icn_ls_mcu,
2992 &ck_flexgen_46),
2993 0, GATE_ADC2, NO_DIV, MUX_ADC2);
2994
2995 static STM32_COMPOSITE(ck_ker_usb2phy1, 2, PARENT(&ck_flexgen_57,
2996 &ck_hse_div2),
2997 0, GATE_USB2PHY1, NO_DIV, MUX_USB2PHY1);
2998
2999 static STM32_COMPOSITE(ck_ker_usb2phy2_en, 2, PARENT(&ck_flexgen_58,
3000 &ck_hse_div2),
3001 0, GATE_USB2PHY2, NO_DIV, MUX_USB2PHY2);
3002
3003 static STM32_COMPOSITE(ck_ker_dts, 3, PARENT(&ck_hsi, &ck_hse, &ck_msi),
3004 0, GATE_DTS, NO_DIV, MUX_DTS);
3005
3006 enum {
3007 CK_OFF = STM32MP21_LAST_CLK,
3008 I2SCKIN,
3009 SPDIFSYMB,
3010 CK_HSE_RTC,
3011 CK_OBSER0,
3012 CK_OBSER1,
3013 CK_HSI_KER,
3014 CK_HSE_KER,
3015 CK_MSI_KER,
3016 STM32MP21_ALL_CLK_NB
3017 };
3018
3019 static STM32_GATE(ck_ker_eth1mac, &ck_icn_ls_mcu, 0, GATE_ETH1MAC);
3020 static STM32_GATE(ck_ker_eth1tx, &ck_icn_ls_mcu, 0, GATE_ETH1TX);
3021 static STM32_GATE(ck_ker_eth1rx, &ck_icn_ls_mcu, 0, GATE_ETH1RX);
3022 static STM32_GATE(ck_ker_eth2mac, &ck_icn_ls_mcu, 0, GATE_ETH2MAC);
3023 static STM32_GATE(ck_ker_eth2tx, &ck_icn_ls_mcu, 0, GATE_ETH2TX);
3024 static STM32_GATE(ck_ker_eth2rx, &ck_icn_ls_mcu, 0, GATE_ETH2RX);
3025
3026 static struct clk *stm32mp21_clk_provided[STM32MP21_ALL_CLK_NB] = {
3027 [HSI_CK] = &ck_hsi,
3028 [HSE_CK] = &ck_hse,
3029 [MSI_CK] = &ck_msi,
3030 [LSI_CK] = &ck_lsi,
3031 [LSE_CK] = &ck_lse,
3032
3033 /* Force oscillator for low-power mode with KERON */
3034 [HSI_KER_CK] = &ck_hsi_keron,
3035 [HSE_KER_CK] = &ck_hse_keron,
3036 [MSI_KER_CK] = &ck_msi_keron,
3037
3038 [HSE_DIV2_CK] = &ck_hse_div2,
3039
3040 [PLL1_CK] = &ck_pll1,
3041 [PLL2_CK] = &ck_pll2,
3042 [PLL4_CK] = &ck_pll4,
3043 [PLL5_CK] = &ck_pll5,
3044 [PLL6_CK] = &ck_pll6,
3045 [PLL7_CK] = &ck_pll7,
3046 [PLL8_CK] = &ck_pll8,
3047
3048 [CK_ICN_HS_MCU] = &ck_icn_hs_mcu,
3049 [CK_ICN_LS_MCU] = &ck_icn_ls_mcu,
3050
3051 [CK_ICN_SDMMC] = &ck_icn_sdmmc,
3052 [CK_ICN_DDR] = &ck_icn_ddr,
3053 [CK_ICN_DISPLAY] = &ck_icn_display,
3054 [CK_ICN_HSL] = &ck_icn_hsl,
3055 [CK_ICN_NIC] = &ck_icn_nic,
3056 [CK_FLEXGEN_07] = &ck_flexgen_07,
3057 [CK_FLEXGEN_08] = &ck_flexgen_08,
3058 [CK_FLEXGEN_09] = &ck_flexgen_09,
3059 [CK_FLEXGEN_10] = &ck_flexgen_10,
3060 [CK_FLEXGEN_11] = &ck_flexgen_11,
3061 [CK_FLEXGEN_12] = &ck_flexgen_12,
3062 [CK_FLEXGEN_13] = &ck_flexgen_13,
3063 [CK_FLEXGEN_14] = &ck_flexgen_14,
3064 [CK_FLEXGEN_15] = &ck_flexgen_15,
3065 [CK_FLEXGEN_16] = &ck_flexgen_16,
3066 [CK_FLEXGEN_17] = &ck_flexgen_17,
3067 [CK_FLEXGEN_18] = &ck_flexgen_18,
3068 [CK_FLEXGEN_19] = &ck_flexgen_19,
3069 [CK_FLEXGEN_20] = &ck_flexgen_20,
3070 [CK_FLEXGEN_21] = &ck_flexgen_21,
3071 [CK_FLEXGEN_22] = &ck_flexgen_22,
3072 [CK_FLEXGEN_23] = &ck_flexgen_23,
3073 [CK_FLEXGEN_24] = &ck_flexgen_24,
3074 [CK_FLEXGEN_25] = &ck_flexgen_25,
3075 [CK_FLEXGEN_26] = &ck_flexgen_26,
3076 [CK_FLEXGEN_27] = &ck_flexgen_27,
3077 [CK_FLEXGEN_28] = &ck_flexgen_28,
3078 [CK_FLEXGEN_29] = &ck_flexgen_29,
3079 [CK_FLEXGEN_30] = &ck_flexgen_30,
3080 [CK_FLEXGEN_31] = &ck_flexgen_31,
3081 [CK_FLEXGEN_32] = &ck_flexgen_32,
3082 [CK_FLEXGEN_33] = &ck_flexgen_33,
3083 [CK_FLEXGEN_34] = &ck_flexgen_34,
3084 [CK_FLEXGEN_35] = &ck_flexgen_35,
3085 [CK_FLEXGEN_36] = &ck_flexgen_36,
3086 [CK_FLEXGEN_37] = &ck_flexgen_37,
3087 [CK_FLEXGEN_38] = &ck_flexgen_38,
3088 [CK_FLEXGEN_39] = &ck_flexgen_39,
3089 [CK_FLEXGEN_40] = &ck_flexgen_40,
3090 [CK_FLEXGEN_41] = &ck_flexgen_41,
3091 [CK_FLEXGEN_42] = &ck_flexgen_42,
3092 [CK_FLEXGEN_43] = &ck_flexgen_43,
3093 [CK_FLEXGEN_44] = &ck_flexgen_44,
3094 [CK_FLEXGEN_45] = &ck_flexgen_45,
3095 [CK_FLEXGEN_46] = &ck_flexgen_46,
3096 [CK_FLEXGEN_47] = &ck_flexgen_47,
3097 [CK_FLEXGEN_48] = &ck_flexgen_48,
3098 [CK_FLEXGEN_49] = &ck_flexgen_49,
3099 [CK_FLEXGEN_50] = &ck_flexgen_50,
3100 [CK_FLEXGEN_51] = &ck_flexgen_51,
3101 [CK_FLEXGEN_52] = &ck_flexgen_52,
3102 [CK_FLEXGEN_53] = &ck_flexgen_53,
3103 [CK_FLEXGEN_54] = &ck_flexgen_54,
3104 [CK_FLEXGEN_55] = &ck_flexgen_55,
3105 [CK_FLEXGEN_56] = &ck_flexgen_56,
3106 [CK_FLEXGEN_57] = &ck_flexgen_57,
3107 [CK_FLEXGEN_58] = &ck_flexgen_58,
3108 [CK_FLEXGEN_59] = &ck_flexgen_59,
3109 [CK_FLEXGEN_60] = &ck_flexgen_60,
3110 [CK_FLEXGEN_61] = &ck_flexgen_61,
3111 [CK_FLEXGEN_62] = &ck_flexgen_62,
3112 [CK_FLEXGEN_63] = &ck_flexgen_63,
3113
3114 [CK_CPU1] = &ck_cpu1,
3115
3116 [CK_ICN_APB1] = &ck_icn_apb1,
3117 [CK_ICN_APB2] = &ck_icn_apb2,
3118 [CK_ICN_APB3] = &ck_icn_apb3,
3119 [CK_ICN_APB4] = &ck_icn_apb4,
3120 [CK_ICN_APB5] = &ck_icn_apb5,
3121 [CK_ICN_APBDBG] = &ck_icn_apbdbg,
3122
3123 [TIMG1_CK] = &ck_timg1,
3124 [TIMG2_CK] = &ck_timg2,
3125
3126 [CK_BUS_SYSRAM] = &ck_icn_s_sysram,
3127 [CK_BUS_RETRAM] = &ck_icn_s_retram,
3128 [CK_BUS_SRAM1] = &ck_icn_s_sram1,
3129 [CK_BUS_OSPI1] = &ck_icn_s_ospi1,
3130 [CK_BUS_BKPSRAM] = &ck_icn_s_bkpsram,
3131 [CK_BUS_DDRPHYC] = &ck_icn_p_ddrphyc,
3132 [CK_BUS_SYSCPU1] = &ck_icn_p_syscpu1,
3133 [CK_BUS_HPDMA1] = &ck_icn_p_hpdma1,
3134 [CK_BUS_HPDMA2] = &ck_icn_p_hpdma2,
3135 [CK_BUS_HPDMA3] = &ck_icn_p_hpdma3,
3136 [CK_BUS_IPCC1] = &ck_icn_p_ipcc1,
3137 [CK_BUS_DCMIPSSI] = &ck_icn_p_dcmipssi,
3138 [CK_BUS_CRC] = &ck_icn_p_crc,
3139 [CK_BUS_HASH1] = &ck_icn_p_hash1,
3140 [CK_BUS_HASH2] = &ck_icn_p_hash2,
3141 [CK_BUS_RNG1] = &ck_icn_p_rng1,
3142 [CK_BUS_RNG2] = &ck_icn_p_rng2,
3143 [CK_BUS_CRYP1] = &ck_icn_p_cryp1,
3144 [CK_BUS_CRYP2] = &ck_icn_p_cryp2,
3145 [CK_BUS_SAES] = &ck_icn_p_saes,
3146 [CK_BUS_PKA] = &ck_icn_p_pka,
3147 [CK_BUS_GPIOA] = &ck_icn_p_gpioa,
3148 [CK_BUS_GPIOB] = &ck_icn_p_gpiob,
3149 [CK_BUS_GPIOC] = &ck_icn_p_gpioc,
3150 [CK_BUS_GPIOD] = &ck_icn_p_gpiod,
3151 [CK_BUS_GPIOE] = &ck_icn_p_gpioe,
3152 [CK_BUS_GPIOF] = &ck_icn_p_gpiof,
3153 [CK_BUS_GPIOG] = &ck_icn_p_gpiog,
3154 [CK_BUS_GPIOH] = &ck_icn_p_gpioh,
3155 [CK_BUS_GPIOI] = &ck_icn_p_gpioi,
3156 [CK_BUS_GPIOZ] = &ck_icn_p_gpioz,
3157 [CK_BUS_RTC] = &ck_icn_p_rtc,
3158 [CK_BUS_STM] = &ck_icn_p_stm,
3159 [CK_KER_STM] = &ck_icn_s_stm,
3160 [CK_BUS_FMC] = &ck_icn_p_fmc,
3161 [CK_BUS_ETH1] = &ck_icn_p_eth1,
3162 [CK_BUS_ETH2] = &ck_icn_p_eth2,
3163 [CK_BUS_ADC1] = &ck_icn_p_adc1,
3164 [CK_BUS_ADC2] = &ck_icn_p_adc2,
3165 [CK_BUS_MDF1] = &ck_icn_p_mdf1,
3166 [CK_BUS_LPUART1] = &ck_icn_p_lpuart1,
3167 [CK_BUS_LPTIM3] = &ck_icn_p_lptim3,
3168 [CK_BUS_LPTIM4] = &ck_icn_p_lptim4,
3169 [CK_BUS_LPTIM5] = &ck_icn_p_lptim5,
3170 [CK_BUS_RISAF4] = &ck_icn_p_risaf4,
3171 [CK_BUS_SDMMC1] = &ck_icn_m_sdmmc1,
3172 [CK_BUS_SDMMC2] = &ck_icn_m_sdmmc2,
3173 [CK_BUS_SDMMC3] = &ck_icn_m_sdmmc3,
3174 [CK_BUS_DDR] = &ck_icn_s_ddr,
3175 [CK_BUS_USBHOHCI] = &ck_icn_m_usbhohci,
3176 [CK_BUS_USBHEHCI] = &ck_icn_m_usbhehci,
3177 [CK_BUS_OTG] = &ck_icn_m_otg,
3178 [CK_BUS_TIM2] = &ck_icn_p_tim2,
3179 [CK_BUS_TIM3] = &ck_icn_p_tim3,
3180 [CK_BUS_TIM4] = &ck_icn_p_tim4,
3181 [CK_BUS_TIM5] = &ck_icn_p_tim5,
3182 [CK_BUS_TIM6] = &ck_icn_p_tim6,
3183 [CK_BUS_TIM7] = &ck_icn_p_tim7,
3184 [CK_BUS_TIM10] = &ck_icn_p_tim10,
3185 [CK_BUS_TIM11] = &ck_icn_p_tim11,
3186 [CK_BUS_TIM12] = &ck_icn_p_tim12,
3187 [CK_BUS_TIM13] = &ck_icn_p_tim13,
3188 [CK_BUS_TIM14] = &ck_icn_p_tim14,
3189 [CK_BUS_LPTIM1] = &ck_icn_p_lptim1,
3190 [CK_BUS_LPTIM2] = &ck_icn_p_lptim2,
3191 [CK_BUS_SPI2] = &ck_icn_p_spi2,
3192 [CK_BUS_SPI3] = &ck_icn_p_spi3,
3193 [CK_BUS_SPDIFRX] = &ck_icn_p_spdifrx,
3194 [CK_BUS_USART2] = &ck_icn_p_usart2,
3195 [CK_BUS_USART3] = &ck_icn_p_usart3,
3196 [CK_BUS_UART4] = &ck_icn_p_uart4,
3197 [CK_BUS_UART5] = &ck_icn_p_uart5,
3198 [CK_BUS_I2C1] = &ck_icn_p_i2c1,
3199 [CK_BUS_I2C2] = &ck_icn_p_i2c2,
3200 [CK_BUS_I2C3] = &ck_icn_p_i2c3,
3201 [CK_BUS_I3C1] = &ck_icn_p_i3c1,
3202 [CK_BUS_I3C2] = &ck_icn_p_i3c2,
3203 [CK_BUS_I3C3] = &ck_icn_p_i3c3,
3204 [CK_BUS_TIM1] = &ck_icn_p_tim1,
3205 [CK_BUS_TIM8] = &ck_icn_p_tim8,
3206 [CK_BUS_TIM15] = &ck_icn_p_tim15,
3207 [CK_BUS_TIM16] = &ck_icn_p_tim16,
3208 [CK_BUS_TIM17] = &ck_icn_p_tim17,
3209 [CK_BUS_SAI1] = &ck_icn_p_sai1,
3210 [CK_BUS_SAI2] = &ck_icn_p_sai2,
3211 [CK_BUS_SAI3] = &ck_icn_p_sai3,
3212 [CK_BUS_SAI4] = &ck_icn_p_sai4,
3213 [CK_BUS_USART1] = &ck_icn_p_usart1,
3214 [CK_BUS_USART6] = &ck_icn_p_usart6,
3215 [CK_BUS_UART7] = &ck_icn_p_uart7,
3216 [CK_BUS_FDCAN] = &ck_icn_p_fdcan,
3217 [CK_BUS_SPI1] = &ck_icn_p_spi1,
3218 [CK_BUS_SPI4] = &ck_icn_p_spi4,
3219 [CK_BUS_SPI5] = &ck_icn_p_spi5,
3220 [CK_BUS_SPI6] = &ck_icn_p_spi6,
3221 [CK_BUS_BSEC] = &ck_icn_p_bsec,
3222 [CK_BUS_IWDG1] = &ck_icn_p_iwdg1,
3223 [CK_BUS_IWDG2] = &ck_icn_p_iwdg2,
3224 [CK_BUS_IWDG3] = &ck_icn_p_iwdg3,
3225 [CK_BUS_IWDG4] = &ck_icn_p_iwdg4,
3226 [CK_BUS_WWDG1] = &ck_icn_p_wwdg1,
3227 [CK_BUS_VREF] = &ck_icn_p_vref,
3228 [CK_BUS_SERC] = &ck_icn_p_serc,
3229 [CK_BUS_DTS] = &ck_icn_p_dts,
3230 [CK_BUS_HDP] = &ck_icn_p_hdp,
3231 [CK_BUS_LTDC] = &ck_icn_p_ltdc,
3232 [CK_BUS_CSI] = &ck_icn_p_csi,
3233 [CK_BUS_DCMIPP] = &ck_icn_p_dcmipp,
3234 [CK_BUS_DDRC] = &ck_icn_p_ddrc,
3235 [CK_BUS_DDRCFG] = &ck_icn_p_ddrcfg,
3236 [CK_BUS_DDRPERFM] = &ck_icn_p_ddrperfm,
3237 [CK_BUS_STGEN] = &ck_icn_p_stgen,
3238 [CK_SYSDBG] = &ck_sys_dbg,
3239 [CK_DBGMCU] = &ck_icn_p_dbgmcu,
3240 [CK_DAP] = &ck_dap,
3241 [CK_KER_TIM2] = &ck_ker_tim2,
3242 [CK_KER_TIM3] = &ck_ker_tim3,
3243 [CK_KER_TIM4] = &ck_ker_tim4,
3244 [CK_KER_TIM5] = &ck_ker_tim5,
3245 [CK_KER_TIM6] = &ck_ker_tim6,
3246 [CK_KER_TIM7] = &ck_ker_tim7,
3247 [CK_KER_TIM10] = &ck_ker_tim10,
3248 [CK_KER_TIM11] = &ck_ker_tim11,
3249 [CK_KER_TIM12] = &ck_ker_tim12,
3250 [CK_KER_TIM13] = &ck_ker_tim13,
3251 [CK_KER_TIM14] = &ck_ker_tim14,
3252 [CK_KER_TIM1] = &ck_ker_tim1,
3253 [CK_KER_TIM8] = &ck_ker_tim8,
3254 [CK_KER_TIM15] = &ck_ker_tim15,
3255 [CK_KER_TIM16] = &ck_ker_tim16,
3256 [CK_KER_TIM17] = &ck_ker_tim17,
3257 [CK_KER_LPTIM1] = &ck_ker_lptim1,
3258 [CK_KER_LPTIM2] = &ck_ker_lptim2,
3259 [CK_KER_USART2] = &ck_ker_usart2,
3260 [CK_KER_UART4] = &ck_ker_uart4,
3261 [CK_KER_USART3] = &ck_ker_usart3,
3262 [CK_KER_UART5] = &ck_ker_uart5,
3263 [CK_KER_SPI2] = &ck_ker_spi2,
3264 [CK_KER_SPI3] = &ck_ker_spi3,
3265 [CK_KER_SPDIFRX] = &ck_ker_spdifrx,
3266 [CK_KER_I2C1] = &ck_ker_i2c1,
3267 [CK_KER_I2C2] = &ck_ker_i2c2,
3268 [CK_KER_I3C1] = &ck_ker_i3c1,
3269 [CK_KER_I3C2] = &ck_ker_i3c2,
3270 [CK_KER_I2C3] = &ck_ker_i2c3,
3271 [CK_KER_I3C3] = &ck_ker_i3c3,
3272 [CK_KER_SPI1] = &ck_ker_spi1,
3273 [CK_KER_SPI4] = &ck_ker_spi4,
3274 [CK_KER_SPI5] = &ck_ker_spi5,
3275 [CK_KER_SPI6] = &ck_ker_spi6,
3276 [CK_KER_USART1] = &ck_ker_usart1,
3277 [CK_KER_USART6] = &ck_ker_usart6,
3278 [CK_KER_UART7] = &ck_ker_uart7,
3279 [CK_KER_MDF1] = &ck_ker_mdf1,
3280 [CK_KER_SAI1] = &ck_ker_sai1,
3281 [CK_KER_SAI2] = &ck_ker_sai2,
3282 [CK_KER_SAI3] = &ck_ker_sai3,
3283 [CK_KER_SAI4] = &ck_ker_sai4,
3284 [CK_KER_FDCAN] = &ck_ker_fdcan,
3285 [CK_KER_CSI] = &ck_ker_csi,
3286 [CK_KER_CSITXESC] = &ck_ker_csitxesc,
3287 [CK_KER_CSIPHY] = &ck_ker_csiphy,
3288 [CK_KER_STGEN] = &ck_ker_stgen,
3289 [CK_KER_LPUART1] = &ck_ker_lpuart1,
3290 [CK_KER_LPTIM3] = &ck_ker_lptim3,
3291 [CK_KER_LPTIM4] = &ck_ker_lptim4,
3292 [CK_KER_LPTIM5] = &ck_ker_lptim5,
3293 [CK_KER_TSDBG] = &ck_ker_tsdbg,
3294 [CK_KER_TPIU] = &ck_ker_tpiu,
3295 [CK_BUS_ETR] = &ck_icn_p_etr,
3296 [CK_KER_ETR] = &ck_icn_m_etr,
3297 [CK_BUS_SYSATB] = &ck_sys_atb,
3298 [CK_KER_OSPI1] = &ck_ker_ospi1,
3299 [CK_KER_FMC] = &ck_ker_fmc,
3300 [CK_KER_SDMMC1] = &ck_ker_sdmmc1,
3301 [CK_KER_SDMMC2] = &ck_ker_sdmmc2,
3302 [CK_KER_SDMMC3] = &ck_ker_sdmmc3,
3303 [CK_KER_ETH1] = &ck_ker_eth1,
3304 [CK_ETH1_STP] = &ck_ker_eth1stp,
3305 [CK_KER_ETH2] = &ck_ker_eth2,
3306 [CK_ETH2_STP] = &ck_ker_eth2stp,
3307 [CK_KER_ETH1PTP] = &ck_ker_eth1ptp,
3308 [CK_KER_ETH2PTP] = &ck_ker_eth2ptp,
3309
3310 [CK_MCO1] = &ck_mco1,
3311 [CK_MCO2] = &ck_mco2,
3312 [CK_KER_ADC1] = &ck_ker_adc1,
3313 [CK_KER_ADC2] = &ck_ker_adc2,
3314 [CK_KER_USB2PHY1] = &ck_ker_usb2phy1,
3315 [CK_KER_USB2PHY2EN] = &ck_ker_usb2phy2_en,
3316 [CK_KER_LTDC] = &ck_ker_ltdc,
3317 [CK_KER_DTS] = &ck_ker_dts,
3318 [RTC_CK] = &ck_rtc,
3319
3320 [CK_ETH1_MAC] = &ck_ker_eth1mac,
3321 [CK_ETH1_TX] = &ck_ker_eth1tx,
3322 [CK_ETH1_RX] = &ck_ker_eth1rx,
3323 [CK_ETH2_MAC] = &ck_ker_eth2mac,
3324 [CK_ETH2_TX] = &ck_ker_eth2tx,
3325 [CK_ETH2_RX] = &ck_ker_eth2rx,
3326
3327 /* Internal clocks */
3328 [CK_HSE_RTC] = &ck_hse_rtc,
3329 [CK_OBSER0] = &ck_obser0,
3330 [CK_OBSER1] = &ck_obser1,
3331 [CK_OFF] = &ck_off,
3332 [I2SCKIN] = &i2sckin,
3333 [SPDIFSYMB] = &spdifsymb,
3334 [CK_HSI_KER] = &ck_hsi_ker,
3335 [CK_HSE_KER] = &ck_hse_ker,
3336 [CK_MSI_KER] = &ck_msi_ker,
3337 };
3338
clk_stm32_clock_is_critical(struct clk * clk)3339 static bool clk_stm32_clock_is_critical(struct clk *clk)
3340 {
3341 struct clk *clk_criticals[] = {
3342 &ck_hsi,
3343 &ck_hse,
3344 &ck_msi,
3345 &ck_lsi,
3346 &ck_lse,
3347 &ck_icn_hs_mcu,
3348 &ck_icn_ls_mcu,
3349 &ck_icn_sdmmc,
3350 &ck_icn_ddr,
3351 &ck_icn_display,
3352 &ck_icn_hsl,
3353 &ck_icn_nic,
3354 &ck_flexgen_63,
3355 &ck_cpu1,
3356 &ck_icn_p_syscpu1,
3357 &ck_icn_s_ddr,
3358 &ck_icn_p_ddrc,
3359 &ck_icn_p_ddrcfg,
3360 &ck_icn_p_ddrphyc,
3361 &ck_icn_s_sysram,
3362 &ck_icn_s_bkpsram,
3363 &ck_ker_fmc,
3364 &ck_ker_ospi1,
3365 &ck_icn_p_hpdma1,
3366 &ck_icn_p_hpdma2,
3367 &ck_icn_p_hpdma3,
3368 &ck_icn_p_gpioa,
3369 &ck_icn_p_gpiob,
3370 &ck_icn_p_gpioc,
3371 &ck_icn_p_gpiod,
3372 &ck_icn_p_gpioe,
3373 &ck_icn_p_gpiof,
3374 &ck_icn_p_gpiog,
3375 &ck_icn_p_gpioh,
3376 &ck_icn_p_gpioi,
3377 &ck_icn_p_gpioz,
3378 &ck_icn_p_ipcc1,
3379 };
3380 size_t i = 0;
3381
3382 for (i = 0; i < ARRAY_SIZE(clk_criticals); i++)
3383 if (clk == clk_criticals[i])
3384 return true;
3385 return false;
3386 }
3387
clk_stm32_init_oscillators(const void * fdt,int node)3388 static void clk_stm32_init_oscillators(const void *fdt, int node)
3389 {
3390 size_t i = 0;
3391 static const char * const name[] = {
3392 "clk-hse", "clk-hsi", "clk-lse",
3393 "clk-lsi", "clk-msi", "clk-i2sin"
3394 };
3395 struct clk *clks[ARRAY_SIZE(name)] = {
3396 &ck_hse, &ck_hsi, &ck_lse,
3397 &ck_lsi, &ck_msi, &i2sckin
3398 };
3399
3400 for (i = 0; i < ARRAY_SIZE(clks); i++) {
3401 struct clk *clk = NULL;
3402
3403 if (clk_dt_get_by_name(fdt, node, name[i], &clk))
3404 panic();
3405
3406 clks[i]->parents[0] = clk;
3407 }
3408
3409 ck_hse_ker.parents[0] = ck_hse.parents[0];
3410 ck_hsi_ker.parents[0] = ck_hsi.parents[0];
3411 ck_msi_ker.parents[0] = ck_msi.parents[0];
3412 }
3413
clk_stm32_apply_rcc_config(struct stm32_clk_platdata * pdata)3414 static TEE_Result clk_stm32_apply_rcc_config(struct stm32_clk_platdata *pdata)
3415 {
3416 if (pdata->safe_rst)
3417 stm32mp25_syscfg_set_safe_reset(true);
3418
3419 return TEE_SUCCESS;
3420 }
3421
3422 static struct stm32_pll_dt_cfg mp21_pll[PLL_NB];
3423 static struct stm32_clk_opp_dt_cfg mp21_clk_opp;
3424 static struct stm32_osci_dt_cfg mp21_osci[NB_OSCILLATOR];
3425
3426 #define DT_FLEXGEN_CLK_MAX 64
3427 static uint32_t mp21_flexgen[DT_FLEXGEN_CLK_MAX];
3428
3429 #define DT_BUS_CLK_MAX 7
3430 static uint32_t mp21_busclk[DT_BUS_CLK_MAX];
3431
3432 #define DT_KERNEL_CLK_MAX 20
3433 static uint32_t mp21_kernelclk[DT_KERNEL_CLK_MAX];
3434
3435 static struct stm32_clk_platdata stm32mp21_clock_pdata = {
3436 .osci = mp21_osci,
3437 .nosci = NB_OSCILLATOR,
3438 .pll = mp21_pll,
3439 .npll = PLL_NB,
3440 .opp = &mp21_clk_opp,
3441 .busclk = mp21_busclk,
3442 .nbusclk = DT_BUS_CLK_MAX,
3443 .kernelclk = mp21_kernelclk,
3444 .nkernelclk = DT_KERNEL_CLK_MAX,
3445 .flexgen = mp21_flexgen,
3446 .nflexgen = DT_FLEXGEN_CLK_MAX,
3447 };
3448
3449 static struct clk_stm32_priv stm32mp21_clock_data = {
3450 .muxes = parent_mp21,
3451 .nb_muxes = ARRAY_SIZE(parent_mp21),
3452 .gates = gates_mp21,
3453 .nb_gates = ARRAY_SIZE(gates_mp21),
3454 .div = dividers_mp21,
3455 .nb_div = ARRAY_SIZE(dividers_mp21),
3456 .pdata = &stm32mp21_clock_pdata,
3457 .nb_clk_refs = STM32MP21_ALL_CLK_NB,
3458 .clk_refs = stm32mp21_clk_provided,
3459 .is_critical = clk_stm32_clock_is_critical,
3460 };
3461
is_rcc_rif_reserved(unsigned int id)3462 static bool is_rcc_rif_reserved(unsigned int id)
3463 {
3464 switch (id) {
3465 case 72:
3466 case 79:
3467 case 80:
3468 case 81:
3469 case 82:
3470 case 89:
3471 case 99:
3472 case 100:
3473 case 105:
3474 case 107:
3475 case 111:
3476 return true;
3477 default:
3478 return false;
3479 }
3480 }
3481
handle_available_semaphores(void)3482 static TEE_Result handle_available_semaphores(void)
3483 {
3484 struct stm32_clk_platdata *pdata = &stm32mp21_clock_pdata;
3485 TEE_Result res = TEE_ERROR_GENERIC;
3486 unsigned int index = 0;
3487 uint32_t cidcfgr = 0;
3488 unsigned int i = 0;
3489
3490 for (i = 0; i < RCC_NB_RIF_RES; i++) {
3491 vaddr_t reg_offset = pdata->rcc_base + RCC_SEMCR(i);
3492
3493 index = i / 32;
3494
3495 if (is_rcc_rif_reserved(i) ||
3496 (!(BIT(i % 32) & pdata->conf_data.access_mask[index])))
3497 continue;
3498
3499 cidcfgr = io_read32(pdata->rcc_base + RCC_CIDCFGR(i));
3500
3501 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1))
3502 continue;
3503
3504 if (!(io_read32(pdata->rcc_base + RCC_SECCFGR(index)) &
3505 BIT(i % 32))) {
3506 res = stm32_rif_release_semaphore(reg_offset,
3507 MAX_CID_SUPPORTED);
3508 if (res) {
3509 EMSG("Cannot release semaphore for resource %"PRIu32,
3510 i);
3511 return res;
3512 }
3513 } else {
3514 res = stm32_rif_acquire_semaphore(reg_offset,
3515 MAX_CID_SUPPORTED);
3516 if (res) {
3517 EMSG("Cannot acquire semaphore for resource %"PRIu32,
3518 i);
3519 return res;
3520 }
3521 }
3522 }
3523
3524 return TEE_SUCCESS;
3525 }
3526
apply_rcc_rif_config(bool is_tdcid)3527 static TEE_Result apply_rcc_rif_config(bool is_tdcid)
3528 {
3529 TEE_Result res = TEE_ERROR_ACCESS_DENIED;
3530 struct stm32_clk_platdata *pdata = &stm32mp21_clock_pdata;
3531 unsigned int i = 0;
3532 unsigned int index = 0;
3533
3534 if (is_tdcid) {
3535 for (i = 0; i < RCC_NB_RIF_RES; i++) {
3536 index = i / 32;
3537
3538 if (is_rcc_rif_reserved(i) ||
3539 (!(BIT(i % 32) &
3540 pdata->conf_data.access_mask[index])))
3541 continue;
3542
3543 /*
3544 * When TDCID, OP-TEE should be the one to set the CID
3545 * filtering configuration. Clearing previous
3546 * configuration prevents undesired events during the
3547 * only legitimate configuration.
3548 */
3549 io_clrbits32(pdata->rcc_base + RCC_CIDCFGR(i),
3550 RCC_CIDCFGR_CONF_MASK);
3551 }
3552 } else {
3553 res = handle_available_semaphores();
3554 if (res)
3555 panic();
3556 }
3557
3558 /* Security and privilege RIF configuration */
3559 for (index = 0; index < RCC_NB_CONFS; index++) {
3560 io_clrsetbits32(pdata->rcc_base + RCC_PRIVCFGR(index),
3561 pdata->conf_data.access_mask[index],
3562 pdata->conf_data.priv_conf[index]);
3563 io_clrsetbits32(pdata->rcc_base + RCC_SECCFGR(index),
3564 pdata->conf_data.access_mask[index],
3565 pdata->conf_data.sec_conf[index]);
3566 }
3567
3568 if (!is_tdcid)
3569 goto end;
3570
3571 for (i = 0; i < RCC_NB_RIF_RES; i++) {
3572 index = i / 32;
3573
3574 if (is_rcc_rif_reserved(i) ||
3575 !(BIT(i % 32) & pdata->conf_data.access_mask[index]))
3576 continue;
3577
3578 io_clrsetbits32(pdata->rcc_base + RCC_CIDCFGR(i),
3579 RCC_CIDCFGR_CONF_MASK,
3580 pdata->conf_data.cid_confs[i]);
3581 }
3582
3583 for (index = 0; index < RCC_NB_CONFS; index++) {
3584 io_clrsetbits32(pdata->rcc_base + RCC_RCFGLOCKR(index),
3585 pdata->conf_data.access_mask[index],
3586 pdata->conf_data.lock_conf[index]);
3587 }
3588
3589 res = handle_available_semaphores();
3590 if (res)
3591 panic();
3592 end:
3593 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) {
3594 for (index = 0; index < RCC_NB_CONFS; index++) {
3595 /* Check that RIF config are applied, panic otherwise */
3596 if ((io_read32(pdata->rcc_base + RCC_PRIVCFGR(index)) &
3597 pdata->conf_data.access_mask[index]) !=
3598 pdata->conf_data.priv_conf[index])
3599 panic("rcc resource prv conf is incorrect");
3600
3601 if ((io_read32(pdata->rcc_base + RCC_SECCFGR(index)) &
3602 pdata->conf_data.access_mask[index]) !=
3603 pdata->conf_data.sec_conf[index])
3604 panic("rcc resource sec conf is incorrect");
3605 }
3606 }
3607
3608 return TEE_SUCCESS;
3609 }
3610
stm32_rcc_rif_pm_resume(void)3611 static TEE_Result stm32_rcc_rif_pm_resume(void)
3612 {
3613 return apply_rcc_rif_config(true);
3614 }
3615
stm32_rcc_rif_pm_suspend(void)3616 static TEE_Result stm32_rcc_rif_pm_suspend(void)
3617 {
3618 struct stm32_clk_platdata *pdata = &stm32mp21_clock_pdata;
3619 unsigned int i = 0;
3620
3621 if (!pdata->nb_res)
3622 return TEE_SUCCESS;
3623
3624 for (i = 0; i < RCC_NB_RIF_RES; i++)
3625 pdata->conf_data.cid_confs[i] = io_read32(pdata->rcc_base +
3626 RCC_CIDCFGR(i));
3627
3628 for (i = 0; i < RCC_NB_CONFS; i++) {
3629 pdata->conf_data.priv_conf[i] = io_read32(pdata->rcc_base +
3630 RCC_PRIVCFGR(i));
3631 pdata->conf_data.sec_conf[i] = io_read32(pdata->rcc_base +
3632 RCC_SECCFGR(i));
3633 pdata->conf_data.lock_conf[i] = io_read32(pdata->rcc_base +
3634 RCC_RCFGLOCKR(i));
3635 pdata->conf_data.access_mask[i] = GENMASK_32(31, 0);
3636 }
3637
3638 return TEE_SUCCESS;
3639 }
3640
stm32_rcc_rif_pm(enum pm_op op,unsigned int pm_hint,const struct pm_callback_handle * h __unused)3641 static TEE_Result stm32_rcc_rif_pm(enum pm_op op, unsigned int pm_hint,
3642 const struct pm_callback_handle *h __unused)
3643 {
3644 TEE_Result res = TEE_ERROR_GENERIC;
3645 bool is_tdcid = false;
3646
3647 if (!PM_HINT_IS_STATE(pm_hint, CONTEXT))
3648 return TEE_SUCCESS;
3649
3650 res = stm32_rifsc_check_tdcid(&is_tdcid);
3651 if (res)
3652 return res;
3653
3654 if (op == PM_OP_RESUME) {
3655 if (is_tdcid)
3656 res = stm32_rcc_rif_pm_resume();
3657 else
3658 res = handle_available_semaphores();
3659 } else {
3660 if (!is_tdcid)
3661 return TEE_SUCCESS;
3662
3663 res = stm32_rcc_rif_pm_suspend();
3664 }
3665
3666 return res;
3667 }
3668
rcc_rif_config(void)3669 static TEE_Result rcc_rif_config(void)
3670 {
3671 TEE_Result res = TEE_ERROR_ACCESS_DENIED;
3672 bool is_tdcid = false;
3673
3674 /* Not expected to fail at this stage */
3675 res = stm32_rifsc_check_tdcid(&is_tdcid);
3676 if (res)
3677 panic();
3678
3679 res = apply_rcc_rif_config(is_tdcid);
3680 if (res)
3681 panic();
3682
3683 register_pm_core_service_cb(stm32_rcc_rif_pm, NULL, "stm32-rcc-rif");
3684
3685 return TEE_SUCCESS;
3686 }
3687
3688 driver_init_late(rcc_rif_config);
3689
stm32mp21_clk_probe(const void * fdt,int node,const void * compat_data __unused)3690 static TEE_Result stm32mp21_clk_probe(const void *fdt, int node,
3691 const void *compat_data __unused)
3692 {
3693 TEE_Result res = TEE_ERROR_GENERIC;
3694 int fdt_rc = 0;
3695 int rc = 0;
3696 struct clk_stm32_priv *priv = &stm32mp21_clock_data;
3697 struct stm32_clk_platdata *pdata = &stm32mp21_clock_pdata;
3698 int subnode = 0;
3699
3700 fdt_rc = stm32_clk_parse_fdt(fdt, node, pdata);
3701 if (fdt_rc) {
3702 EMSG("Failed to parse clock node: %d", fdt_rc);
3703 return TEE_ERROR_GENERIC;
3704 }
3705
3706 fdt_for_each_subnode(subnode, fdt, node) {
3707 res = dt_driver_maybe_add_probe_node(fdt, subnode);
3708 if (res) {
3709 EMSG("Failed on node %s with %#"PRIx32,
3710 fdt_get_name(fdt, subnode, NULL), res);
3711 goto err;
3712 }
3713 }
3714
3715 if (IS_ENABLED(CFG_STM32_CM33TDCID)) {
3716 res = handle_available_semaphores();
3717 if (res)
3718 goto err;
3719 }
3720
3721 rc = clk_stm32_init(priv, stm32_rcc_base());
3722 if (rc) {
3723 res = TEE_ERROR_GENERIC;
3724 goto err;
3725 }
3726
3727 stm32mp2_init_clock_tree(priv, pdata);
3728
3729 clk_stm32_init_oscillators(fdt, node);
3730
3731 res = clk_stm32_apply_rcc_config(pdata);
3732 if (res)
3733 panic("Error when applying RCC config");
3734
3735 stm32mp_clk_provider_probe_final(fdt, node, priv);
3736
3737 if (IS_ENABLED(CFG_STM32_CLK_DEBUG))
3738 clk_print_tree();
3739
3740 return TEE_SUCCESS;
3741 err:
3742 free(pdata->conf_data.cid_confs);
3743 free(pdata->conf_data.sec_conf);
3744 free(pdata->conf_data.priv_conf);
3745 free(pdata->conf_data.lock_conf);
3746 free(pdata->conf_data.access_mask);
3747
3748 return res;
3749 }
3750
3751 CLK_DT_DECLARE(stm32mp21_clk, "st,stm32mp21-rcc", stm32mp21_clk_probe);
3752