1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2017-2024, STMicroelectronics
4 *
5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs.
6 */
7
8 #include <assert.h>
9 #include <compiler.h>
10 #include <drivers/clk.h>
11 #include <drivers/clk_dt.h>
12 #include <drivers/firewall.h>
13 #include <drivers/gpio.h>
14 #include <drivers/pinctrl.h>
15 #include <drivers/stm32_gpio.h>
16 #include <drivers/stm32_rif.h>
17 #include <dt-bindings/gpio/stm32mp_gpio.h>
18 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
19 #include <io.h>
20 #include <kernel/dt.h>
21 #include <kernel/boot.h>
22 #include <kernel/panic.h>
23 #include <kernel/pm.h>
24 #include <kernel/spinlock.h>
25 #include <libfdt.h>
26 #include <mm/core_memprot.h>
27 #include <stdbool.h>
28 #include <stdint.h>
29 #include <stm32_util.h>
30 #include <sys/queue.h>
31 #include <trace.h>
32 #include <util.h>
33
34 #define GPIO_PIN_MAX 15
35
36 #define GPIO_MODER_OFFSET U(0x00)
37 #define GPIO_OTYPER_OFFSET U(0x04)
38 #define GPIO_OSPEEDR_OFFSET U(0x08)
39 #define GPIO_PUPDR_OFFSET U(0x0c)
40 #define GPIO_IDR_OFFSET U(0x10)
41 #define GPIO_ODR_OFFSET U(0x14)
42 #define GPIO_BSRR_OFFSET U(0x18)
43 #define GPIO_AFRL_OFFSET U(0x20)
44 #define GPIO_AFRH_OFFSET U(0x24)
45 #define GPIO_SECR_OFFSET U(0x30)
46 #define GPIO_PRIVCFGR_OFFSET U(0x34)
47 #define GPIO_RCFGLOCKR_OFFSET U(0x38)
48 #define GPIO_CIDCFGR(x) (U(0x50) + U(0x8) * (x))
49 #define GPIO_SEMCR(x) (U(0x54) + U(0x8) * (x))
50
51 #define GPIO_ALT_LOWER_LIMIT U(0x8)
52
53 /*
54 * CIDCFGR register bitfields
55 */
56 #define GPIO_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16)
57 #define GPIO_CIDCFGR_SCID_MASK GENMASK_32(6, 4)
58 #define GPIO_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | _CIDCFGR_SEMEN | \
59 GPIO_CIDCFGR_SCID_MASK | \
60 GPIO_CIDCFGR_SEMWL_MASK)
61
62 /*
63 * PRIVCFGR register bitfields
64 */
65 #define GPIO_PRIVCFGR_MASK GENMASK_32(15, 0)
66
67 /*
68 * SECCFGR register bitfields
69 */
70 #define GPIO_SECCFGR_MASK GENMASK_32(15, 0)
71
72 /*
73 * RCFGLOCKR register bitfields
74 */
75 #define GPIO_RCFGLOCKR_MASK GENMASK_32(15, 0)
76
77 /*
78 * SEMCR register bitfields
79 */
80 #define GPIO_SEMCR_SCID_M GENMASK_32(6, 4)
81
82 #define GPIO_MODE_MASK GENMASK_32(1, 0)
83 #define GPIO_OSPEED_MASK GENMASK_32(1, 0)
84 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0)
85 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0)
86
87 #define DT_GPIO_BANK_SHIFT U(12)
88 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12)
89 #define DT_GPIO_PIN_SHIFT U(8)
90 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8)
91 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0)
92
93 #define DT_GPIO_BANK_NAME0 "GPIOA"
94
95 #define GPIO_MODE_INPUT U(0x0)
96 #define GPIO_MODE_OUTPUT U(0x1)
97 #define GPIO_MODE_ALTERNATE U(0x2)
98 #define GPIO_MODE_ANALOG U(0x3)
99
100 #define GPIO_OTYPE_PUSH_PULL U(0x0)
101 #define GPIO_OTYPE_OPEN_DRAIN U(0x1)
102
103 #define GPIO_OSPEED_LOW U(0x0)
104 #define GPIO_OSPEED_MEDIUM U(0x1)
105 #define GPIO_OSPEED_HIGH U(0x2)
106 #define GPIO_OSPEED_VERY_HIGH U(0x3)
107
108 #define GPIO_PUPD_NO_PULL U(0x0)
109 #define GPIO_PUPD_PULL_UP U(0x1)
110 #define GPIO_PUPD_PULL_DOWN U(0x2)
111
112 #define GPIO_OD_LEVEL_LOW U(0x0)
113 #define GPIO_OD_LEVEL_HIGH U(0x1)
114
115 #define GPIO_MAX_CID_SUPPORTED U(3)
116
117 /*
118 * GPIO configuration description structured as single 16bit word
119 * for efficient save/restore when GPIO pin suspends or resumes.
120 *
121 * @mode: One of GPIO_MODE_*
122 * @otype: One of GPIO_OTYPE_*
123 * @ospeed: One of GPIO_OSPEED_*
124 * @pupd: One of GPIO_PUPD_*
125 * @od: One of GPIO_OD_*
126 * @af: Alternate function numerical ID between 0 and 15
127 * @nsec: Hint on expected secure state of the pin: 0 if secure, 1 otherwise
128 */
129 struct gpio_cfg {
130 uint16_t mode: 2;
131 uint16_t otype: 1;
132 uint16_t ospeed: 2;
133 uint16_t pupd: 2;
134 uint16_t od: 1;
135 uint16_t af: 4;
136 uint16_t nsec: 1;
137 };
138
139 /*
140 * Description of a pin and its muxing
141 *
142 * @bank: GPIO bank identifier as assigned by the platform
143 * @pin: Pin number in the GPIO bank
144 * @cfg: Pin configuration
145 */
146 struct stm32_pinctrl {
147 uint8_t bank;
148 uint8_t pin;
149 struct gpio_cfg cfg;
150 };
151
152 /*
153 * struct stm32_pinctrl_array - Array of pins in a pin control state
154 * @count: Number of cells in @pinctrl
155 * @pinctrl: Pin control configuration
156 */
157 struct stm32_pinctrl_array {
158 size_t count;
159 struct stm32_pinctrl pinctrl[];
160 };
161
162 /**
163 * struct stm32_gpio_bank - GPIO bank instance
164 *
165 * @base: base address of the GPIO controller registers.
166 * @clock: clock identifier.
167 * @gpio_chip: GPIO chip reference for that GPIO bank
168 * @ngpios: number of GPIOs.
169 * @bank_id: Id of the bank.
170 * @lock: lock protecting the GPIO bank access.
171 * @rif_cfg: RIF configuration data
172 * @seccfgr: non-RIF bank secure configuration data
173 * @sec_support: True if bank supports pin security protection, else false
174 * @ready: True if configuration is applied, else false
175 * @is_tdcid: True if OP-TEE runs as Trusted Domain CID
176 * @link: Link in bank list
177 */
178 struct stm32_gpio_bank {
179 vaddr_t base;
180 struct clk *clock;
181 struct gpio_chip gpio_chip;
182 unsigned int ngpios;
183 unsigned int bank_id;
184 unsigned int lock;
185 struct rif_conf_data *rif_cfg;
186 uint32_t seccfgr;
187 bool sec_support;
188 bool ready;
189 bool is_tdcid;
190 STAILQ_ENTRY(stm32_gpio_bank) link;
191 };
192
193 /*
194 * struct stm32_gpio_pm_state - Consumed GPIO for PM purpose
195 * @gpio_pinctrl: Reference and configuration state for a consumed GPIO
196 * @level: GPIO level
197 * @link: Link in consumed GPIO list
198 */
199 struct stm32_gpio_pm_state {
200 struct stm32_pinctrl gpio_pinctrl;
201 uint8_t level;
202 SLIST_ENTRY(stm32_gpio_pm_state) link;
203 };
204
205 /**
206 * Compatibility information of supported banks
207 *
208 * @gpioz: True if bank is a GPIOZ bank
209 * @secure_control: Identify GPIO security bank capability.
210 * @secure_extended: Identify RIF presence.
211 */
212 struct bank_compat {
213 bool gpioz;
214 bool secure_control;
215 bool secure_extended;
216 };
217
218 static unsigned int gpio_lock;
219
220 static STAILQ_HEAD(, stm32_gpio_bank) bank_list =
221 STAILQ_HEAD_INITIALIZER(bank_list);
222
223 static SLIST_HEAD(, stm32_gpio_pm_state) consumed_gpios_head;
224
225 static bool is_stm32_gpio_chip(struct gpio_chip *chip);
226
gpio_chip_to_bank(struct gpio_chip * chip)227 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip)
228 {
229 return container_of(chip, struct stm32_gpio_bank, gpio_chip);
230 }
231
stm32_gpio_chip_bank_id(struct gpio_chip * chip)232 unsigned int stm32_gpio_chip_bank_id(struct gpio_chip *chip)
233 {
234 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);
235
236 return bank->bank_id;
237 }
238
stm32_gpio_get_level(struct gpio_chip * chip,unsigned int gpio_pin)239 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip,
240 unsigned int gpio_pin)
241 {
242 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);
243 enum gpio_level level = GPIO_LEVEL_HIGH;
244 unsigned int reg_offset = 0;
245 unsigned int mode = 0;
246
247 assert(gpio_pin < bank->ngpios);
248
249 if (clk_enable(bank->clock))
250 panic();
251
252 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) &
253 GPIO_MODE_MASK;
254
255 switch (mode) {
256 case GPIO_MODE_INPUT:
257 reg_offset = GPIO_IDR_OFFSET;
258 break;
259 case GPIO_MODE_OUTPUT:
260 reg_offset = GPIO_ODR_OFFSET;
261 break;
262 default:
263 panic();
264 }
265
266 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin))
267 level = GPIO_LEVEL_HIGH;
268 else
269 level = GPIO_LEVEL_LOW;
270
271 clk_disable(bank->clock);
272
273 return level;
274 }
275
stm32_gpio_set_level(struct gpio_chip * chip,unsigned int gpio_pin,enum gpio_level level)276 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin,
277 enum gpio_level level)
278 {
279 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);
280
281 assert(gpio_pin < bank->ngpios);
282
283 if (clk_enable(bank->clock))
284 panic();
285
286 if (level == GPIO_LEVEL_HIGH)
287 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin));
288 else
289 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16));
290
291 clk_disable(bank->clock);
292 }
293
stm32_gpio_get_direction(struct gpio_chip * chip,unsigned int gpio_pin)294 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip,
295 unsigned int gpio_pin)
296 {
297 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);
298 uint32_t mode = 0;
299
300 assert(gpio_pin < bank->ngpios);
301
302 if (clk_enable(bank->clock))
303 panic();
304
305 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) &
306 GPIO_MODE_MASK;
307
308 clk_disable(bank->clock);
309
310 switch (mode) {
311 case GPIO_MODE_INPUT:
312 return GPIO_DIR_IN;
313 case GPIO_MODE_OUTPUT:
314 return GPIO_DIR_OUT;
315 default:
316 panic();
317 }
318 }
319
stm32_gpio_set_direction(struct gpio_chip * chip,unsigned int gpio_pin,enum gpio_dir direction)320 static void stm32_gpio_set_direction(struct gpio_chip *chip,
321 unsigned int gpio_pin,
322 enum gpio_dir direction)
323 {
324 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);
325 uint32_t exceptions = 0;
326 uint32_t mode = 0;
327
328 assert(gpio_pin < bank->ngpios);
329
330 if (direction == GPIO_DIR_IN)
331 mode = GPIO_MODE_INPUT;
332 else
333 mode = GPIO_MODE_OUTPUT;
334
335 if (clk_enable(bank->clock))
336 panic();
337 exceptions = cpu_spin_lock_xsave(&gpio_lock);
338 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET,
339 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1),
340 SHIFT_U32(mode, gpio_pin << 1));
341 cpu_spin_unlock_xrestore(&gpio_lock, exceptions);
342 clk_disable(bank->clock);
343 }
344
345 /* Forward reference to the PM callback handler for consumed GPIOs */
346 static TEE_Result consumed_gpios_pm(enum pm_op op, unsigned int pm_hint,
347 const struct pm_callback_handle *pm_hdl);
348
349 /* Forward reference to RIF semaphore release helper function */
350 static void release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank,
351 unsigned int pin);
352
stm32_gpio_configure(struct gpio_chip * chip,struct gpio * gpio)353 static TEE_Result stm32_gpio_configure(struct gpio_chip *chip,
354 struct gpio *gpio)
355 {
356 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);
357 uint32_t exceptions = 0;
358 uint32_t otype = 0;
359 uint32_t pupd = 0;
360 unsigned int shift_1b = gpio->pin;
361 unsigned int shift_2b = SHIFT_U32(gpio->pin, 1);
362
363 assert(is_stm32_gpio_chip(chip));
364
365 if (gpio->dt_flags & GPIO_PULL_UP)
366 pupd = GPIO_PUPD_PULL_UP;
367 else if (gpio->dt_flags & GPIO_PULL_DOWN)
368 pupd = GPIO_PUPD_PULL_DOWN;
369 else
370 pupd = GPIO_PUPD_NO_PULL;
371
372 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN)
373 otype = GPIO_OTYPE_OPEN_DRAIN;
374 else
375 otype = GPIO_OTYPE_PUSH_PULL;
376
377 if (clk_enable(bank->clock))
378 panic();
379 exceptions = cpu_spin_lock_xsave(&gpio_lock);
380
381 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET,
382 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b),
383 SHIFT_U32(otype, shift_1b));
384
385 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET,
386 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b),
387 SHIFT_U32(pupd, shift_2b));
388
389 cpu_spin_unlock_xrestore(&gpio_lock, exceptions);
390 clk_disable(bank->clock);
391
392 return TEE_SUCCESS;
393 }
394
stm32_gpio_put_gpio(struct gpio_chip * chip,struct gpio * gpio)395 static void stm32_gpio_put_gpio(struct gpio_chip *chip, struct gpio *gpio)
396 {
397 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);
398 struct stm32_gpio_pm_state *tstate = NULL;
399 struct stm32_gpio_pm_state *state = NULL;
400 uint32_t exceptions = 0;
401
402 assert(is_stm32_gpio_chip(chip));
403
404 exceptions = cpu_spin_lock_xsave(&gpio_lock);
405
406 SLIST_FOREACH_SAFE(state, &consumed_gpios_head, link, tstate) {
407 if (state->gpio_pinctrl.bank == bank->bank_id &&
408 state->gpio_pinctrl.pin == gpio->pin) {
409 SLIST_REMOVE(&consumed_gpios_head, state,
410 stm32_gpio_pm_state, link);
411 unregister_pm_driver_cb(consumed_gpios_pm, state);
412 release_rif_semaphore_if_acquired(bank, gpio->pin);
413 free(state);
414 free(gpio);
415 break;
416 }
417 }
418 assert(state);
419
420 cpu_spin_unlock_xrestore(&gpio_lock, exceptions);
421 }
422
423 static const struct gpio_ops stm32_gpio_ops = {
424 .get_direction = stm32_gpio_get_direction,
425 .set_direction = stm32_gpio_set_direction,
426 .get_value = stm32_gpio_get_level,
427 .set_value = stm32_gpio_set_level,
428 .configure = stm32_gpio_configure,
429 .put = stm32_gpio_put_gpio,
430 };
431
is_stm32_gpio_chip(struct gpio_chip * chip)432 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip)
433 {
434 return chip && chip->ops == &stm32_gpio_ops;
435 }
436
stm32_gpio_get_bank(unsigned int bank_id)437 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id)
438 {
439 struct stm32_gpio_bank *bank = NULL;
440
441 STAILQ_FOREACH(bank, &bank_list, link)
442 if (bank_id == bank->bank_id)
443 return bank;
444
445 panic();
446 }
447
448 #if defined(CFG_STM32_RIF)
pin_is_accessible(struct stm32_gpio_bank * bank,unsigned int pin)449 static bool pin_is_accessible(struct stm32_gpio_bank *bank, unsigned int pin)
450 {
451 bool accessible = false;
452 uint32_t cidcfgr = 0;
453
454 if (!bank->rif_cfg)
455 return true;
456
457 if (clk_enable(bank->clock))
458 panic();
459
460 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin));
461
462 if (!(cidcfgr & _CIDCFGR_CFEN)) {
463 /* Resource can be accessed when CID filtering is disabled */
464 accessible = true;
465 } else if (stm32_rif_scid_ok(cidcfgr, GPIO_CIDCFGR_SCID_MASK,
466 RIF_CID1)) {
467 /* Resource can be accessed if CID1 is statically allowed */
468 accessible = true;
469 } else if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) {
470 /* CID1 is allowed to request the semaphore */
471 accessible = true;
472 }
473
474 clk_disable(bank->clock);
475
476 return accessible;
477 }
478
acquire_rif_semaphore_if_needed(struct stm32_gpio_bank * bank,unsigned int pin)479 static TEE_Result acquire_rif_semaphore_if_needed(struct stm32_gpio_bank *bank,
480 unsigned int pin)
481 {
482 TEE_Result res = TEE_SUCCESS;
483 uint32_t cidcfgr = 0;
484
485 if (!bank->rif_cfg)
486 return TEE_SUCCESS;
487
488 res = clk_enable(bank->clock);
489 if (res)
490 return res;
491
492 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin));
493
494 if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1))
495 res = stm32_rif_acquire_semaphore(bank->base + GPIO_SEMCR(pin),
496 GPIO_MAX_CID_SUPPORTED);
497
498 clk_disable(bank->clock);
499
500 return res;
501 }
502
semaphore_current_cid(struct stm32_gpio_bank * bank,unsigned int pin)503 static uint32_t semaphore_current_cid(struct stm32_gpio_bank *bank,
504 unsigned int pin)
505 {
506 return (io_read32(bank->base + GPIO_SEMCR(pin)) >>
507 _CIDCFGR_SCID_SHIFT) &
508 GENMASK_32(GPIO_MAX_CID_SUPPORTED - 1, 0);
509 }
510
release_rif_semaphore_if_acquired(struct stm32_gpio_bank * bank,unsigned int pin)511 static void release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank,
512 unsigned int pin)
513 {
514 TEE_Result res = TEE_ERROR_GENERIC;
515 uint32_t cidcfgr = 0;
516
517 if (!bank->rif_cfg)
518 return;
519
520 res = clk_enable(bank->clock);
521 if (res)
522 panic();
523
524 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin));
525
526 if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1) &&
527 semaphore_current_cid(bank, pin) == RIF_CID1) {
528 res = stm32_rif_release_semaphore(bank->base + GPIO_SEMCR(pin),
529 GPIO_MAX_CID_SUPPORTED);
530 if (res) {
531 EMSG("Failed to release GPIO %c%u semaphore",
532 bank->bank_id + 'A', pin);
533 panic();
534 }
535 }
536
537 clk_disable(bank->clock);
538 }
539 #else
pin_is_accessible(struct stm32_gpio_bank * bank __unused,unsigned int pin __unused)540 static bool pin_is_accessible(struct stm32_gpio_bank *bank __unused,
541 unsigned int pin __unused)
542 {
543 return true;
544 }
545
546 static TEE_Result
acquire_rif_semaphore_if_needed(struct stm32_gpio_bank * bank __unused,unsigned int pin __unused)547 acquire_rif_semaphore_if_needed(struct stm32_gpio_bank *bank __unused,
548 unsigned int pin __unused)
549 {
550 return TEE_SUCCESS;
551 }
552
553 static void
release_rif_semaphore_if_acquired(struct stm32_gpio_bank * bank __unused,unsigned int pin __unused)554 release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank __unused,
555 unsigned int pin __unused)
556 {
557 }
558 #endif /*CFG_STM32_RIF*/
559
pin_is_secure(struct stm32_gpio_bank * bank,unsigned int pin)560 static bool pin_is_secure(struct stm32_gpio_bank *bank, unsigned int pin)
561 {
562 bool secure = false;
563
564 if (bank->rif_cfg || bank->sec_support) {
565 if (clk_enable(bank->clock))
566 panic();
567
568 secure = io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(pin);
569
570 clk_disable(bank->clock);
571 }
572
573 return secure;
574 }
575
576 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */
get_gpio_cfg(uint32_t bank_id,uint32_t pin,struct gpio_cfg * cfg)577 static void get_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg)
578 {
579 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id);
580
581 if (clk_enable(bank->clock))
582 panic();
583
584 /*
585 * Save GPIO configuration bits spread over the few bank registers.
586 * 1bit fields are accessed at bit position being the pin index.
587 * 2bit fields are accessed at bit position being twice the pin index.
588 * 4bit fields are accessed at bit position being fourth the pin index
589 * but accessed from 2 32bit registers at incremental addresses.
590 */
591 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) &
592 GPIO_MODE_MASK;
593
594 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1;
595
596 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >>
597 (pin << 1)) & GPIO_OSPEED_MASK;
598
599 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) &
600 GPIO_PUPD_PULL_MASK;
601
602 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1;
603
604 if (pin < GPIO_ALT_LOWER_LIMIT)
605 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >>
606 (pin << 2)) & GPIO_ALTERNATE_MASK;
607 else
608 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >>
609 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) &
610 GPIO_ALTERNATE_MASK;
611
612 clk_disable(bank->clock);
613 }
614
615 /* Apply GPIO (@bank/@pin) configuration described by @cfg */
set_gpio_cfg(uint32_t bank_id,uint32_t pin,struct gpio_cfg * cfg)616 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg)
617 {
618 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id);
619 uint32_t exceptions = 0;
620
621 if (clk_enable(bank->clock))
622 panic();
623 exceptions = cpu_spin_lock_xsave(&gpio_lock);
624
625 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */
626 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET,
627 SHIFT_U32(GPIO_MODE_MASK, pin << 1),
628 SHIFT_U32(cfg->mode, pin << 1));
629
630 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */
631 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin),
632 SHIFT_U32(cfg->otype, pin));
633
634 /* Load GPIO Output Speed confguration, 2bit value */
635 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET,
636 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1),
637 SHIFT_U32(cfg->ospeed, pin << 1));
638
639 /* Load GPIO pull configuration, 2bit value */
640 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin),
641 SHIFT_U32(cfg->pupd, pin << 1));
642
643 /* Load pin mux Alternate Function configuration, 4bit value */
644 if (pin < GPIO_ALT_LOWER_LIMIT) {
645 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET,
646 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2),
647 SHIFT_U32(cfg->af, pin << 2));
648 } else {
649 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2;
650
651 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET,
652 SHIFT_U32(GPIO_ALTERNATE_MASK, shift),
653 SHIFT_U32(cfg->af, shift));
654 }
655
656 /* Load GPIO Output direction confuguration, 1bit */
657 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin);
658
659 cpu_spin_unlock_xrestore(&gpio_lock, exceptions);
660 clk_disable(bank->clock);
661 }
662
663 /* Count pins described in the DT node and get related data if possible */
get_pinctrl_from_fdt(const void * fdt,int node,int consumer_node __maybe_unused,struct stm32_pinctrl * pinctrl,size_t count)664 static int get_pinctrl_from_fdt(const void *fdt, int node,
665 int consumer_node __maybe_unused,
666 struct stm32_pinctrl *pinctrl, size_t count)
667 {
668 struct stm32_gpio_bank *bank_ref = NULL;
669 const fdt32_t *cuint = NULL;
670 const fdt32_t *slewrate = NULL;
671 int len = 0;
672 uint32_t i = 0;
673 uint32_t speed = GPIO_OSPEED_LOW;
674 uint32_t pull = GPIO_PUPD_NO_PULL;
675 size_t found = 0;
676 bool do_panic = false;
677
678 cuint = fdt_getprop(fdt, node, "pinmux", &len);
679 if (!cuint)
680 return -FDT_ERR_NOTFOUND;
681
682 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL);
683 if (slewrate)
684 speed = fdt32_to_cpu(*slewrate);
685
686 if (fdt_getprop(fdt, node, "bias-pull-up", NULL))
687 pull = GPIO_PUPD_PULL_UP;
688 if (fdt_getprop(fdt, node, "bias-pull-down", NULL))
689 pull = GPIO_PUPD_PULL_DOWN;
690
691 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) {
692 uint32_t pincfg = 0;
693 uint32_t bank = 0;
694 uint32_t pin = 0;
695 uint32_t mode = 0;
696 uint32_t alternate = 0;
697 uint32_t odata = 0;
698 bool opendrain = false;
699 bool pin_non_secure = true;
700
701 pincfg = fdt32_to_cpu(*cuint);
702 cuint++;
703
704 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT;
705
706 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT;
707
708 mode = pincfg & DT_GPIO_MODE_MASK;
709
710 pin_non_secure = pincfg & STM32_PIN_NSEC;
711
712 switch (mode) {
713 case 0:
714 mode = GPIO_MODE_INPUT;
715 break;
716 case 1:
717 case 2:
718 case 3:
719 case 4:
720 case 5:
721 case 6:
722 case 7:
723 case 8:
724 case 9:
725 case 10:
726 case 11:
727 case 12:
728 case 13:
729 case 14:
730 case 15:
731 case 16:
732 alternate = mode - 1U;
733 mode = GPIO_MODE_ALTERNATE;
734 break;
735 case 17:
736 mode = GPIO_MODE_ANALOG;
737 break;
738 default:
739 mode = GPIO_MODE_OUTPUT;
740 break;
741 }
742
743 if (fdt_getprop(fdt, node, "drive-open-drain", NULL))
744 opendrain = true;
745
746 if (fdt_getprop(fdt, node, "output-high", NULL) &&
747 mode == GPIO_MODE_INPUT) {
748 mode = GPIO_MODE_OUTPUT;
749 odata = 1;
750 }
751
752 if (fdt_getprop(fdt, node, "output-low", NULL) &&
753 mode == GPIO_MODE_INPUT) {
754 mode = GPIO_MODE_OUTPUT;
755 odata = 0;
756 }
757
758 if (found < count) {
759 struct stm32_pinctrl *ref = &pinctrl[found];
760
761 ref->bank = (uint8_t)bank;
762 ref->pin = (uint8_t)pin;
763 ref->cfg.mode = mode;
764 if (opendrain)
765 ref->cfg.otype = GPIO_OTYPE_OPEN_DRAIN;
766 else
767 ref->cfg.otype = GPIO_OTYPE_PUSH_PULL;
768 ref->cfg.ospeed = speed;
769 ref->cfg.pupd = pull;
770 ref->cfg.od = odata;
771 ref->cfg.af = alternate;
772 ref->cfg.nsec = pin_non_secure;
773
774 bank_ref = stm32_gpio_get_bank(bank);
775
776 if (pin >= bank_ref->ngpios) {
777 EMSG("node %s requests pin %c%u that does not exist",
778 fdt_get_name(fdt, consumer_node, NULL),
779 bank + 'A', pin);
780 do_panic = true;
781 }
782 }
783
784 found++;
785 }
786
787 if (do_panic)
788 panic();
789
790 return (int)found;
791 }
792
consumed_gpios_pm(enum pm_op op,unsigned int pm_hint __unused,const struct pm_callback_handle * pm_hdl)793 static TEE_Result consumed_gpios_pm(enum pm_op op,
794 unsigned int pm_hint __unused,
795 const struct pm_callback_handle *pm_hdl)
796 {
797 struct stm32_gpio_pm_state *handle = pm_hdl->handle;
798 unsigned int bank_id = handle->gpio_pinctrl.bank;
799 unsigned int pin = handle->gpio_pinctrl.pin;
800 struct gpio_chip *chip = &stm32_gpio_get_bank(bank_id)->gpio_chip;
801
802 if (op == PM_OP_RESUME) {
803 set_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg);
804 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT)
805 stm32_gpio_set_level(chip, pin, handle->level);
806 } else {
807 get_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg);
808 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT)
809 handle->level = stm32_gpio_get_level(chip, pin);
810 }
811
812 return TEE_SUCCESS;
813 }
814 DECLARE_KEEP_PAGER(consumed_gpios_pm);
815
stm32_gpio_get_dt(struct dt_pargs * pargs,void * data,struct gpio ** out_gpio)816 static TEE_Result stm32_gpio_get_dt(struct dt_pargs *pargs, void *data,
817 struct gpio **out_gpio)
818 {
819 TEE_Result res = TEE_ERROR_GENERIC;
820 const char *consumer_name __maybe_unused = NULL;
821 struct stm32_gpio_pm_state *reg_state = NULL;
822 struct stm32_gpio_pm_state *state = NULL;
823 struct stm32_gpio_bank *bank = data;
824 struct gpio *gpio = NULL;
825 bool gpio_secure = true;
826
827 consumer_name = fdt_get_name(pargs->fdt, pargs->consumer_node,
828 NULL);
829
830 res = gpio_dt_alloc_pin(pargs, &gpio);
831 if (res)
832 return res;
833
834 if (gpio->pin >= bank->ngpios) {
835 DMSG("Invalid GPIO reference");
836 free(gpio);
837 return TEE_ERROR_GENERIC;
838 }
839
840 if (gpio->dt_flags & GPIO_STM32_NSEC)
841 gpio_secure = false;
842
843 state = calloc(1, sizeof(*state));
844 if (!state) {
845 free(gpio);
846 return TEE_ERROR_OUT_OF_MEMORY;
847 }
848
849 SLIST_FOREACH(reg_state, &consumed_gpios_head, link) {
850 if (reg_state->gpio_pinctrl.bank == bank->bank_id &&
851 reg_state->gpio_pinctrl.pin == gpio->pin) {
852 EMSG("node %s: GPIO %c%u is used by another device",
853 consumer_name, bank->bank_id + 'A', gpio->pin);
854 free(state);
855 free(gpio);
856 return TEE_ERROR_GENERIC;
857 }
858 }
859
860 if (!pin_is_accessible(bank, gpio->pin)) {
861 EMSG("node %s requests pin on GPIO %c%u which access is denied",
862 consumer_name, bank->bank_id + 'A', gpio->pin);
863 panic();
864 }
865
866 res = acquire_rif_semaphore_if_needed(bank, gpio->pin);
867 if (res) {
868 EMSG("Failed to acquire GPIO %c%u semaphore for node %s",
869 bank->bank_id + 'A', gpio->pin, consumer_name);
870 return res;
871 }
872
873 if (gpio_secure && !(bank->rif_cfg || bank->sec_support)) {
874 EMSG("node %s requests secure GPIO %c%u that cannot be secured",
875 consumer_name, bank->bank_id + 'A', gpio->pin);
876 panic();
877 }
878
879 if (gpio_secure != pin_is_secure(bank, gpio->pin)) {
880 IMSG("WARNING: node %s requests %s GPIO %c%u but pin is %s. Check st,protreg in GPIO bank node %s",
881 consumer_name, gpio_secure ? "secure" : "non-secure",
882 bank->bank_id + 'A', gpio->pin,
883 pin_is_secure(bank, gpio->pin) ? "secure" : "non-secure",
884 fdt_get_name(pargs->fdt, pargs->phandle_node, NULL));
885 if (!IS_ENABLED(CFG_INSECURE))
886 panic();
887 }
888
889 state->gpio_pinctrl.pin = gpio->pin;
890 state->gpio_pinctrl.bank = bank->bank_id;
891 SLIST_INSERT_HEAD(&consumed_gpios_head, state, link);
892
893 register_pm_driver_cb(consumed_gpios_pm, state, "stm32-gpio-state");
894
895 gpio->chip = &bank->gpio_chip;
896
897 *out_gpio = gpio;
898
899 return TEE_SUCCESS;
900 }
901
902 /* Get bank ID from bank node property st,bank-name or panic on failure */
dt_get_bank_id(const void * fdt,int node)903 static unsigned int dt_get_bank_id(const void *fdt, int node)
904 {
905 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0);
906 const fdt32_t *cuint = NULL;
907 int len = 0;
908
909 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */
910 cuint = fdt_getprop(fdt, node, "st,bank-name", &len);
911 if (!cuint || (len != dt_name_len + 1))
912 panic("Missing/wrong st,bank-name property");
913
914 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) ||
915 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0)
916 panic("Wrong st,bank-name property");
917
918 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0);
919 }
920
921 /*
922 * Return whether or not the GPIO bank related to a DT node is already
923 * registered in the GPIO bank link.
924 */
bank_is_registered(const void * fdt,int node)925 static bool bank_is_registered(const void *fdt, int node)
926 {
927 unsigned int bank_id = dt_get_bank_id(fdt, node);
928 struct stm32_gpio_bank *bank = NULL;
929
930 STAILQ_FOREACH(bank, &bank_list, link)
931 if (bank->bank_id == bank_id)
932 return true;
933
934 return false;
935 }
936
937 #ifdef CFG_STM32_RIF
handle_available_semaphores(struct stm32_gpio_bank * bank,uint32_t gpios_mask)938 static TEE_Result handle_available_semaphores(struct stm32_gpio_bank *bank,
939 uint32_t gpios_mask)
940 {
941 TEE_Result res = TEE_ERROR_GENERIC;
942 uint32_t cidcfgr = 0;
943 unsigned int i = 0;
944
945 for (i = 0 ; i < bank->ngpios; i++) {
946 if (!(BIT(i) & gpios_mask))
947 continue;
948
949 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(i));
950
951 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1))
952 continue;
953
954 if (!(io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(i))) {
955 res = stm32_rif_release_semaphore(bank->base +
956 GPIO_SEMCR(i),
957 MAX_CID_SUPPORTED);
958 if (res) {
959 EMSG("Cannot release semaphore for resource %u",
960 i);
961 return res;
962 }
963 } else {
964 res = stm32_rif_acquire_semaphore(bank->base +
965 GPIO_SEMCR(i),
966 MAX_CID_SUPPORTED);
967 if (res) {
968 EMSG("Cannot acquire semaphore for resource %u",
969 i);
970 return res;
971 }
972 }
973 }
974
975 return TEE_SUCCESS;
976 }
977
apply_rif_config(struct stm32_gpio_bank * bank,uint32_t gpios_mask)978 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank,
979 uint32_t gpios_mask)
980 {
981 TEE_Result res = TEE_ERROR_GENERIC;
982 unsigned int i = 0;
983
984 if (!bank->rif_cfg)
985 return TEE_SUCCESS;
986
987 if (clk_enable(bank->clock))
988 panic();
989
990 if (bank->is_tdcid) {
991 for (i = 0; i < bank->ngpios; i++) {
992 if (!(BIT(i) & gpios_mask))
993 continue;
994
995 /*
996 * When TDCID, OP-TEE should be the one to set the CID
997 * filtering configuration. Clearing previous
998 * configuration prevents undesired events during the
999 * only legitimate configuration.
1000 */
1001 io_clrbits32(bank->base + GPIO_CIDCFGR(i),
1002 GPIO_CIDCFGR_CONF_MASK);
1003 }
1004 } else {
1005 res = handle_available_semaphores(bank, gpios_mask);
1006 if (res)
1007 panic();
1008 }
1009
1010 /* Security and privilege RIF configuration */
1011 io_mask32(bank->base + GPIO_PRIVCFGR_OFFSET,
1012 bank->rif_cfg->priv_conf[0], gpios_mask);
1013 io_mask32(bank->base + GPIO_SECR_OFFSET,
1014 bank->rif_cfg->sec_conf[0], gpios_mask);
1015
1016 if (!bank->is_tdcid) {
1017 res = TEE_SUCCESS;
1018 goto out;
1019 }
1020
1021 for (i = 0; i < bank->ngpios; i++) {
1022 if (!(BIT(i) & gpios_mask))
1023 continue;
1024
1025 io_clrsetbits32(bank->base + GPIO_CIDCFGR(i),
1026 GPIO_CIDCFGR_CONF_MASK,
1027 bank->rif_cfg->cid_confs[i]);
1028 }
1029
1030 /*
1031 * Lock RIF configuration if configured. This cannot be undone until
1032 * next reset.
1033 */
1034 io_setbits32(bank->base + GPIO_RCFGLOCKR_OFFSET,
1035 bank->rif_cfg->lock_conf[0]);
1036
1037 res = handle_available_semaphores(bank, gpios_mask);
1038 if (res)
1039 panic();
1040
1041 out:
1042 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) {
1043 /* Check that RIF config are applied, panic otherwise */
1044 if ((io_read32(bank->base + GPIO_PRIVCFGR_OFFSET) &
1045 gpios_mask) !=
1046 (bank->rif_cfg->priv_conf[0] & gpios_mask)) {
1047 EMSG("GPIO bank%c priv conf is incorrect",
1048 'A' + bank->bank_id);
1049 panic();
1050 }
1051
1052 if ((io_read32(bank->base + GPIO_SECR_OFFSET) & gpios_mask) !=
1053 (bank->rif_cfg->sec_conf[0] & gpios_mask)) {
1054 EMSG("GPIO bank %c sec conf is incorrect",
1055 'A' + bank->bank_id);
1056 panic();
1057 }
1058 }
1059
1060 clk_disable(bank->clock);
1061
1062 return res;
1063 }
1064 #else /* CFG_STM32_RIF */
apply_rif_config(struct stm32_gpio_bank * bank __unused,uint32_t gpios_mask __unused)1065 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank __unused,
1066 uint32_t gpios_mask __unused)
1067 {
1068 return TEE_SUCCESS;
1069 }
1070 #endif /* CFG_STM32_RIF */
1071
1072 /* Forward reference to stm32_gpio_set_conf_sec() defined below */
1073 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank);
1074
stm32_gpio_fw_configure(struct firewall_query * firewall)1075 static TEE_Result stm32_gpio_fw_configure(struct firewall_query *firewall)
1076 {
1077 struct stm32_gpio_bank *bank = firewall->ctrl->priv;
1078 uint32_t firewall_arg = 0;
1079 uint32_t gpios_mask = 0;
1080 bool secure = true;
1081
1082 assert(bank->sec_support);
1083
1084 if (firewall->arg_count != 1)
1085 return TEE_ERROR_BAD_PARAMETERS;
1086
1087 firewall_arg = firewall->args[0];
1088
1089 if (bank->rif_cfg) {
1090 gpios_mask = BIT(RIF_CHANNEL_ID(firewall_arg));
1091
1092 /* We're about to change a specific GPIO config */
1093 bank->rif_cfg->access_mask[0] |= gpios_mask;
1094
1095 /*
1096 * Update bank RIF config with firewall configuration data
1097 * and apply it.
1098 */
1099 stm32_rif_parse_cfg(firewall_arg, bank->rif_cfg,
1100 bank->ngpios);
1101 return apply_rif_config(bank, gpios_mask);
1102 }
1103
1104 /*
1105 * Non RIF GPIO banks use a single cell as a bit mask (bits 0 to 15)
1106 * to define the a group of GPIO pins (one or several) to configure
1107 * for that bank, and GPIO_STM32_NSEC bit flag to set if these pins
1108 * are non-secure (flag set) or non-secure (flag cleared).
1109 */
1110 gpios_mask = firewall_arg & GENMASK_32(15, 0);
1111
1112 secure = !(firewall_arg & GPIO_STM32_NSEC);
1113
1114 if (gpios_mask & ~GENMASK_32(bank->ngpios, 0)) {
1115 EMSG("Invalid bitmask %#"PRIx32" for GPIO bank %c",
1116 gpios_mask, 'A' + bank->bank_id);
1117 return TEE_ERROR_GENERIC;
1118 }
1119
1120 /* Update bank secure register configuration data and apply it */
1121 if (secure)
1122 bank->seccfgr |= gpios_mask;
1123 else
1124 bank->seccfgr &= ~gpios_mask;
1125
1126 stm32_gpio_set_conf_sec(bank);
1127
1128 return TEE_SUCCESS;
1129 }
1130
1131 static const struct firewall_controller_ops stm32_gpio_firewall_ops = {
1132 .set_conf = stm32_gpio_fw_configure,
1133 };
1134
stm32_gpio_save_rif_config(struct stm32_gpio_bank * bank)1135 static void stm32_gpio_save_rif_config(struct stm32_gpio_bank *bank)
1136 {
1137 size_t i = 0;
1138
1139 for (i = 0; i < bank->ngpios; i++)
1140 bank->rif_cfg->cid_confs[i] = io_read32(bank->base +
1141 GPIO_CIDCFGR(i));
1142
1143 bank->rif_cfg->priv_conf[0] = io_read32(bank->base +
1144 GPIO_PRIVCFGR_OFFSET);
1145 bank->rif_cfg->sec_conf[0] = io_read32(bank->base +
1146 GPIO_SECR_OFFSET);
1147 bank->rif_cfg->lock_conf[0] = io_read32(bank->base +
1148 GPIO_RCFGLOCKR_OFFSET);
1149 }
1150
stm32_parse_gpio_rif_conf(struct stm32_gpio_bank * bank,const void * fdt,int node)1151 static void stm32_parse_gpio_rif_conf(struct stm32_gpio_bank *bank,
1152 const void *fdt, int node)
1153 {
1154 unsigned int i = 0;
1155 unsigned int nb_rif_conf = 0;
1156 int lenp = 0;
1157 const fdt32_t *cuint = NULL;
1158
1159 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp);
1160 if (!cuint) {
1161 DMSG("No RIF configuration available");
1162 return;
1163 }
1164
1165 bank->rif_cfg = calloc(1, sizeof(*bank->rif_cfg));
1166 if (!bank->rif_cfg)
1167 panic();
1168
1169 bank->rif_cfg->sec_conf = calloc(1, sizeof(uint32_t));
1170 if (!bank->rif_cfg->sec_conf)
1171 panic();
1172
1173 nb_rif_conf = MIN((unsigned int)(lenp / sizeof(uint32_t)),
1174 bank->ngpios);
1175
1176 bank->rif_cfg->cid_confs = calloc(bank->ngpios, sizeof(uint32_t));
1177 bank->rif_cfg->priv_conf = calloc(1, sizeof(uint32_t));
1178 bank->rif_cfg->lock_conf = calloc(1, sizeof(uint32_t));
1179 bank->rif_cfg->access_mask = calloc(1, sizeof(uint32_t));
1180 if (!bank->rif_cfg->cid_confs || !bank->rif_cfg->access_mask ||
1181 !bank->rif_cfg->priv_conf || !bank->rif_cfg->lock_conf)
1182 panic("Missing memory capacity for GPIOS RIF configuration");
1183
1184 for (i = 0; i < nb_rif_conf; i++)
1185 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), bank->rif_cfg,
1186 bank->ngpios);
1187 }
1188
1189 /* Get GPIO bank information from the DT */
dt_stm32_gpio_bank(const void * fdt,int node,const void * compat_data,int range_offset,struct stm32_gpio_bank ** out_bank)1190 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node,
1191 const void *compat_data,
1192 int range_offset,
1193 struct stm32_gpio_bank **out_bank)
1194 {
1195 const struct bank_compat *compat = compat_data;
1196 TEE_Result res = TEE_ERROR_GENERIC;
1197 struct stm32_gpio_bank *bank = NULL;
1198 const fdt32_t *cuint = NULL;
1199 struct io_pa_va pa_va = { };
1200 struct clk *clk = NULL;
1201 size_t blen = 0;
1202 paddr_t pa = 0;
1203 int len = 0;
1204 int i = 0;
1205
1206 assert(out_bank);
1207
1208 /* Probe deferrable devices first */
1209 res = clk_dt_get_by_index(fdt, node, 0, &clk);
1210 if (res)
1211 return res;
1212
1213 bank = calloc(1, sizeof(*bank));
1214 if (!bank)
1215 return TEE_ERROR_OUT_OF_MEMORY;
1216
1217 if (compat->secure_extended) {
1218 res = stm32_rifsc_check_tdcid(&bank->is_tdcid);
1219 if (res) {
1220 free(bank);
1221 return res;
1222 }
1223 }
1224
1225 /*
1226 * Do not rely *only* on the "reg" property to get the address,
1227 * but consider also the "ranges" translation property
1228 */
1229 if (fdt_reg_info(fdt, node, &pa, &blen))
1230 panic("missing reg or reg size property");
1231
1232 pa_va.pa = pa + range_offset;
1233
1234 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL));
1235 bank->bank_id = dt_get_bank_id(fdt, node);
1236 bank->clock = clk;
1237 bank->gpio_chip.ops = &stm32_gpio_ops;
1238 bank->sec_support = compat->secure_control;
1239
1240 /* Parse gpio-ranges with its 4 parameters */
1241 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len);
1242 len /= sizeof(*cuint);
1243 if (len % 4)
1244 panic("wrong gpio-ranges syntax");
1245
1246 /* Get the last defined gpio line (offset + nb of pins) */
1247 for (i = 0; i < len / 4; i++) {
1248 bank->ngpios = MAX(bank->ngpios,
1249 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) +
1250 fdt32_to_cpu(*(cuint + 3))));
1251 cuint += 4;
1252 }
1253
1254 if (compat->secure_extended) {
1255 /* RIF configuration */
1256 bank->base = io_pa_or_va_secure(&pa_va, blen);
1257
1258 stm32_parse_gpio_rif_conf(bank, fdt, node);
1259 } else if (bank->sec_support) {
1260 /* Secure configuration */
1261 bank->base = io_pa_or_va_secure(&pa_va, blen);
1262 cuint = fdt_getprop(fdt, node, "st,protreg", NULL);
1263 if (cuint)
1264 bank->seccfgr = fdt32_to_cpu(*cuint);
1265 else
1266 DMSG("GPIO bank %c assigned to non-secure",
1267 bank->bank_id + 'A');
1268 } else {
1269 bank->base = io_pa_or_va_nsec(&pa_va, blen);
1270 }
1271
1272 *out_bank = bank;
1273
1274 return TEE_SUCCESS;
1275 }
1276
stm32_gpio_firewall_register(const void * fdt,int node,struct stm32_gpio_bank * bank)1277 static TEE_Result stm32_gpio_firewall_register(const void *fdt, int node,
1278 struct stm32_gpio_bank *bank)
1279 {
1280 struct firewall_controller *controller = NULL;
1281 TEE_Result res = TEE_ERROR_GENERIC;
1282 char bank_name[] = "gpio-bank-X";
1283 char *name = NULL;
1284
1285 if (!IS_ENABLED(CFG_DRIVERS_FIREWALL) ||
1286 !bank->sec_support)
1287 return TEE_SUCCESS;
1288
1289 controller = calloc(1, sizeof(*controller));
1290 if (!controller)
1291 return TEE_ERROR_OUT_OF_MEMORY;
1292
1293 bank_name[sizeof(bank_name) - 2] = 'A' + bank->bank_id;
1294 name = strdup(bank_name);
1295
1296 controller->name = name;
1297 controller->priv = bank;
1298 controller->ops = &stm32_gpio_firewall_ops;
1299
1300 if (!controller->name)
1301 EMSG("Warning: out of memory to store bank name");
1302
1303 res = firewall_dt_controller_register(fdt, node, controller);
1304 if (res) {
1305 free(name);
1306 free(controller);
1307 }
1308
1309 return res;
1310 }
1311
1312 /* Parse a pinctrl node to register the GPIO banks it describes */
dt_stm32_gpio_pinctrl(const void * fdt,int node,const void * compat_data)1313 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node,
1314 const void *compat_data)
1315 {
1316 TEE_Result res = TEE_SUCCESS;
1317 const fdt32_t *cuint = NULL;
1318 int range_offs = 0;
1319 int b_node = 0;
1320 int len = 0;
1321
1322 /* Read the ranges property (for regs memory translation) */
1323 cuint = fdt_getprop(fdt, node, "ranges", &len);
1324 if (!cuint)
1325 panic("missing ranges property");
1326
1327 len /= sizeof(*cuint);
1328 if (len == 3)
1329 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint);
1330
1331 fdt_for_each_subnode(b_node, fdt, node) {
1332 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len);
1333 if (cuint) {
1334 /*
1335 * We found a property "gpio-controller" in the node:
1336 * the node is a GPIO bank description, add it to the
1337 * bank list.
1338 */
1339 struct stm32_gpio_bank *bank = NULL;
1340
1341 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED ||
1342 bank_is_registered(fdt, b_node))
1343 continue;
1344
1345 res = dt_stm32_gpio_bank(fdt, b_node, compat_data,
1346 range_offs, &bank);
1347 if (res)
1348 return res;
1349
1350 /* Registering a provider should not defer probe */
1351 res = gpio_register_provider(fdt, b_node,
1352 stm32_gpio_get_dt, bank);
1353 if (res)
1354 panic();
1355
1356 res = stm32_gpio_firewall_register(fdt, b_node, bank);
1357 if (res)
1358 panic();
1359
1360 STAILQ_INSERT_TAIL(&bank_list, bank, link);
1361 } else {
1362 if (len != -FDT_ERR_NOTFOUND)
1363 panic();
1364 }
1365 }
1366
1367 return TEE_SUCCESS;
1368 }
1369
1370 #ifdef CFG_DRIVERS_PINCTRL
stm32_pinctrl_conf_apply(struct pinconf * conf)1371 static TEE_Result stm32_pinctrl_conf_apply(struct pinconf *conf)
1372 {
1373 struct stm32_pinctrl_array *ref = conf->priv;
1374 struct stm32_pinctrl *p = ref->pinctrl;
1375 struct stm32_gpio_bank *bank = NULL;
1376 TEE_Result res = TEE_ERROR_GENERIC;
1377 size_t pin_count = ref->count;
1378 size_t n = 0;
1379 bool error = false;
1380
1381 for (n = 0; n < pin_count; n++) {
1382 bank = stm32_gpio_get_bank(p[n].bank);
1383
1384 if (!pin_is_accessible(bank, p[n].pin)) {
1385 EMSG("Apply pinctrl for pin %c%u that cannot be accessed",
1386 p[n].bank + 'A', p[n].pin);
1387 error = true;
1388 continue;
1389 }
1390
1391 res = acquire_rif_semaphore_if_needed(bank, p[n].pin);
1392 if (res) {
1393 EMSG("Failed to acquire GPIO %c%u semaphore",
1394 bank->bank_id + 'A', p[n].pin);
1395 error = true;
1396 continue;
1397 }
1398
1399 if (p[n].cfg.nsec == !pin_is_secure(bank, p[n].pin))
1400 continue;
1401
1402 if (IS_ENABLED(CFG_INSECURE)) {
1403 IMSG("WARNING: apply pinctrl for %ssecure pin %c%u that is %ssecure",
1404 p[n].cfg.nsec ? "non-" : "",
1405 p[n].bank + 'A', p[n].pin,
1406 pin_is_secure(bank, p[n].pin) ? "" : "non-");
1407 } else {
1408 EMSG("Apply pinctrl for %ssecure pin %c%u that is %ssecure",
1409 p[n].cfg.nsec ? "non-" : "",
1410 p[n].bank + 'A', p[n].pin,
1411 pin_is_secure(bank, p[n].pin) ? "" : "non-");
1412 error = true;
1413 }
1414 }
1415
1416 if (error) {
1417 for (n = 0; n < pin_count; n++) {
1418 bank = stm32_gpio_get_bank(p[n].bank);
1419 release_rif_semaphore_if_acquired(bank, p[n].pin);
1420 }
1421
1422 return TEE_ERROR_SECURITY;
1423 }
1424
1425 for (n = 0; n < pin_count; n++)
1426 set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg);
1427
1428 return TEE_SUCCESS;
1429 }
1430
stm32_pinctrl_conf_free(struct pinconf * conf)1431 static void stm32_pinctrl_conf_free(struct pinconf *conf)
1432 {
1433 free(conf);
1434 }
1435
1436 static const struct pinctrl_ops stm32_pinctrl_ops = {
1437 .conf_apply = stm32_pinctrl_conf_apply,
1438 .conf_free = stm32_pinctrl_conf_free,
1439 };
1440
1441 DECLARE_KEEP_PAGER(stm32_pinctrl_ops);
1442
stm32_gpio_pinctrl_bank_pin(struct pinctrl_state * pinctrl,unsigned int * bank,unsigned int * pin,unsigned int * count)1443 void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl,
1444 unsigned int *bank, unsigned int *pin,
1445 unsigned int *count)
1446 {
1447 size_t conf_index = 0;
1448 size_t pin_count = 0;
1449 size_t n = 0;
1450
1451 assert(count);
1452 if (!pinctrl)
1453 goto out;
1454
1455 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) {
1456 struct pinconf *pinconf = pinctrl->confs[conf_index];
1457 struct stm32_pinctrl_array *ref = pinconf->priv;
1458
1459 /* Consider only the stm32_gpio pins */
1460 if (pinconf->ops != &stm32_pinctrl_ops)
1461 continue;
1462
1463 if (bank || pin) {
1464 for (n = 0; n < ref->count; n++) {
1465 if (bank && pin_count < *count)
1466 bank[pin_count] = ref->pinctrl[n].bank;
1467 if (pin && pin_count < *count)
1468 pin[pin_count] = ref->pinctrl[n].pin;
1469 pin_count++;
1470 }
1471 } else {
1472 pin_count += ref->count;
1473 }
1474 }
1475
1476 out:
1477 *count = pin_count;
1478 }
1479
1480 /* Allocate and return a pinctrl configuration from a DT reference */
stm32_pinctrl_dt_get(struct dt_pargs * pargs,void * data __unused,struct pinconf ** out_pinconf)1481 static TEE_Result stm32_pinctrl_dt_get(struct dt_pargs *pargs,
1482 void *data __unused,
1483 struct pinconf **out_pinconf)
1484 {
1485 struct conf {
1486 struct pinconf pinconf;
1487 struct stm32_pinctrl_array array_ref;
1488 } *loc_conf = NULL;
1489 struct stm32_pinctrl *pinctrl = NULL;
1490 struct pinconf *pinconf = NULL;
1491 const void *fdt = NULL;
1492 size_t pin_count = 0;
1493 int pinctrl_node = 0;
1494 int pinmux_node = 0;
1495 int count = 0;
1496
1497 pinctrl_node = pargs->phandle_node;
1498 fdt = pargs->fdt;
1499 assert(fdt && pinctrl_node);
1500
1501 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) {
1502 if (fdt_getprop(fdt, pinmux_node, "pinmux", &count))
1503 pin_count += (size_t)count / sizeof(uint32_t);
1504 else if (count != -FDT_ERR_NOTFOUND)
1505 panic();
1506 }
1507
1508 loc_conf = calloc(1, sizeof(*loc_conf) + sizeof(*pinctrl) * pin_count);
1509 if (!loc_conf)
1510 return TEE_ERROR_OUT_OF_MEMORY;
1511
1512 pinconf = &loc_conf->pinconf;
1513 pinconf->ops = &stm32_pinctrl_ops;
1514 pinconf->priv = &loc_conf->array_ref;
1515
1516 loc_conf->array_ref.count = pin_count;
1517 pinctrl = loc_conf->array_ref.pinctrl;
1518
1519 count = 0;
1520 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) {
1521 int found = 0;
1522
1523 found = get_pinctrl_from_fdt(fdt, pinmux_node,
1524 pargs->consumer_node,
1525 pinctrl + count,
1526 pin_count - count);
1527 if (found <= 0 && found > ((int)pin_count - count)) {
1528 /* We can't recover from an error here so let's panic */
1529 panic();
1530 }
1531
1532 count += found;
1533 }
1534
1535 *out_pinconf = pinconf;
1536
1537 return TEE_SUCCESS;
1538 }
1539 #endif /*CFG_DRIVERS_PINCTRL*/
1540
stm32_gpio_get_conf_sec(struct stm32_gpio_bank * bank)1541 static void stm32_gpio_get_conf_sec(struct stm32_gpio_bank *bank)
1542 {
1543 if (bank->sec_support) {
1544 clk_enable(bank->clock);
1545 bank->seccfgr = io_read32(bank->base + GPIO_SECR_OFFSET);
1546 clk_disable(bank->clock);
1547 }
1548 }
1549
stm32_gpio_set_conf_sec(struct stm32_gpio_bank * bank)1550 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank)
1551 {
1552 if (bank->sec_support) {
1553 clk_enable(bank->clock);
1554 io_write32(bank->base + GPIO_SECR_OFFSET, bank->seccfgr);
1555 clk_disable(bank->clock);
1556 }
1557 }
1558
stm32_gpio_sec_config_resume(void)1559 static TEE_Result stm32_gpio_sec_config_resume(void)
1560 {
1561 TEE_Result res = TEE_ERROR_GENERIC;
1562 struct stm32_gpio_bank *bank = NULL;
1563
1564 STAILQ_FOREACH(bank, &bank_list, link) {
1565 if (bank->rif_cfg) {
1566 if (!bank->is_tdcid)
1567 continue;
1568
1569 bank->rif_cfg->access_mask[0] = GENMASK_32(bank->ngpios,
1570 0);
1571
1572 res = apply_rif_config(bank,
1573 bank->rif_cfg->access_mask[0]);
1574 if (res) {
1575 EMSG("Failed to set GPIO bank %c RIF config",
1576 'A' + bank->bank_id);
1577 return res;
1578 }
1579 } else {
1580 stm32_gpio_set_conf_sec(bank);
1581 }
1582 }
1583
1584 return TEE_SUCCESS;
1585 }
1586
stm32_gpio_sec_config_suspend(void)1587 static TEE_Result stm32_gpio_sec_config_suspend(void)
1588 {
1589 struct stm32_gpio_bank *bank = NULL;
1590
1591 STAILQ_FOREACH(bank, &bank_list, link) {
1592 if (bank->rif_cfg) {
1593 if (bank->is_tdcid)
1594 stm32_gpio_save_rif_config(bank);
1595 } else {
1596 stm32_gpio_get_conf_sec(bank);
1597 }
1598 }
1599
1600 return TEE_SUCCESS;
1601 }
1602
1603 static TEE_Result
stm32_gpio_sec_config_pm(enum pm_op op,unsigned int pm_hint,const struct pm_callback_handle * hdl __unused)1604 stm32_gpio_sec_config_pm(enum pm_op op, unsigned int pm_hint,
1605 const struct pm_callback_handle *hdl __unused)
1606 {
1607 TEE_Result ret = TEE_ERROR_GENERIC;
1608
1609 if (!PM_HINT_IS_STATE(pm_hint, CONTEXT))
1610 return TEE_SUCCESS;
1611
1612 if (op == PM_OP_RESUME)
1613 ret = stm32_gpio_sec_config_resume();
1614 else
1615 ret = stm32_gpio_sec_config_suspend();
1616
1617 return ret;
1618 }
1619 DECLARE_KEEP_PAGER(stm32_gpio_sec_config_pm);
1620
1621 /*
1622 * Several pinctrl nodes can be probed. Their bank will be put in the unique
1623 * bank_list. To avoid multiple configuration set for a bank when looping
1624 * over each bank in the bank list, ready is set to true when a bank is
1625 * configured. Therefore, during other bank probes, the configuration won't
1626 * be set again.
1627 */
apply_sec_cfg(void)1628 static TEE_Result apply_sec_cfg(void)
1629 {
1630 TEE_Result res = TEE_ERROR_GENERIC;
1631 struct stm32_gpio_bank *bank = NULL;
1632 unsigned int pin = 0;
1633
1634 STAILQ_FOREACH(bank, &bank_list, link) {
1635 if (bank->ready)
1636 continue;
1637
1638 if (bank->rif_cfg) {
1639 res = apply_rif_config(bank,
1640 bank->rif_cfg->access_mask[0]);
1641 if (res) {
1642 EMSG("Failed to set GPIO bank %c RIF config",
1643 'A' + bank->bank_id);
1644 STAILQ_REMOVE(&bank_list, bank, stm32_gpio_bank,
1645 link);
1646 free(bank);
1647 return res;
1648 }
1649
1650 /*
1651 * Semaphores for pinctrl and GPIO are taken when
1652 * these are used (pinctrl state applied, GPIO
1653 * consumed) or when an explicit firewall configuration
1654 * is requested through the firewall framework.
1655 * Therefore release here the taken semaphores.
1656 */
1657 for (pin = 0; pin < bank->ngpios; pin++)
1658 release_rif_semaphore_if_acquired(bank, pin);
1659
1660 } else {
1661 stm32_gpio_set_conf_sec(bank);
1662 }
1663
1664 bank->ready = true;
1665 }
1666
1667 return TEE_SUCCESS;
1668 }
1669
stm32_pinctrl_probe(const void * fdt,int node,const void * compat_data)1670 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node,
1671 const void *compat_data)
1672 {
1673 static bool pm_register;
1674 TEE_Result res = TEE_ERROR_GENERIC;
1675
1676 /* Register GPIO banks described in this pin control node */
1677 res = dt_stm32_gpio_pinctrl(fdt, node, compat_data);
1678 if (res)
1679 return res;
1680
1681 if (STAILQ_EMPTY(&bank_list))
1682 DMSG("no gpio bank for that driver");
1683 else if (apply_sec_cfg())
1684 panic();
1685
1686 if (!pm_register) {
1687 /*
1688 * Register to PM once for all probed banks to restore
1689 * their secure configuration.
1690 */
1691 register_pm_driver_cb(stm32_gpio_sec_config_pm, NULL,
1692 "stm32-gpio-secure-config");
1693 pm_register = true;
1694 }
1695
1696 #ifdef CFG_DRIVERS_PINCTRL
1697 res = pinctrl_register_provider(fdt, node, stm32_pinctrl_dt_get,
1698 (void *)compat_data);
1699 if (res)
1700 panic();
1701 #endif
1702
1703 return TEE_SUCCESS;
1704 }
1705
1706 static const struct dt_device_match stm32_pinctrl_match_table[] = {
1707 {
1708 .compatible = "st,stm32mp135-pinctrl",
1709 .compat_data = &(struct bank_compat){
1710 .secure_control = true,
1711 .secure_extended = false,
1712 },
1713 },
1714 {
1715 .compatible = "st,stm32mp157-pinctrl",
1716 .compat_data = &(struct bank_compat){
1717 .secure_control = false,
1718 .secure_extended = false,
1719 },
1720 },
1721 {
1722 .compatible = "st,stm32mp157-z-pinctrl",
1723 .compat_data = &(struct bank_compat){
1724 .gpioz = true,
1725 .secure_control = true,
1726 .secure_extended = false,
1727 },
1728 },
1729 {
1730 .compatible = "st,stm32mp257-pinctrl",
1731 .compat_data = &(struct bank_compat){
1732 .secure_control = true,
1733 .secure_extended = true,
1734 },
1735 },
1736 {
1737 .compatible = "st,stm32mp257-z-pinctrl",
1738 .compat_data = &(struct bank_compat){
1739 .gpioz = true,
1740 .secure_control = true,
1741 .secure_extended = true,
1742 },
1743 },
1744 { }
1745 };
1746
1747 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = {
1748 .name = "stm32_gpio-pinctrl",
1749 .type = DT_DRIVER_PINCTRL,
1750 .match_table = stm32_pinctrl_match_table,
1751 .probe = stm32_pinctrl_probe,
1752 };
1753