1 /*
2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <bl31/interrupt_mgmt.h>
15 #include <drivers/console.h>
16 #include <lib/xlat_tables/xlat_tables_v2.h>
17 #include <plat/common/platform.h>
18
19 #include <rpi_hw.h>
20 #include <rpi_shared.h>
21
22 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
23 DEVICE0_SIZE, \
24 MT_DEVICE | MT_RW | MT_SECURE)
25
26 #ifdef SHARED_RAM_BASE
27 #define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \
28 SHARED_RAM_SIZE, \
29 MT_DEVICE | MT_RW | MT_SECURE)
30 #endif
31
32 #ifdef RPI3_PRELOADED_DTB_BASE
33 #define MAP_NS_DTB MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \
34 MT_MEMORY | MT_RW | MT_NS)
35 #endif
36
37 #define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \
38 MT_MEMORY | MT_RW | MT_NS)
39 #ifdef FW_HANDOFF_BASE
40 #define MAP_FW_HANDOFF MAP_REGION_FLAT(FW_HANDOFF_BASE, FW_HANDOFF_SIZE, \
41 MT_MEMORY | MT_RW | EL3_PAS)
42 #endif
43 #define MAP_FIP MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE, \
44 PLAT_RPI3_FIP_MAX_SIZE, \
45 MT_MEMORY | MT_RO | MT_NS)
46
47 #define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \
48 MT_MEMORY | MT_RW | MT_SECURE)
49
50 #ifdef SPD_opteed
51 #define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \
52 RPI3_OPTEE_PAGEABLE_LOAD_BASE, \
53 RPI3_OPTEE_PAGEABLE_LOAD_SIZE, \
54 MT_MEMORY | MT_RW | MT_SECURE)
55 #endif
56
57 /*
58 * Table of regions for various BL stages to map using the MMU.
59 */
60 #ifdef IMAGE_BL1
61 static const mmap_region_t plat_rpi3_mmap[] = {
62 #ifdef MAP_SHARED_RAM
63 /* Mapping used by both legacy convention and firmware handoff*/
64 MAP_SHARED_RAM,
65 #endif
66 MAP_DEVICE0,
67 MAP_FIP,
68 #ifdef SPD_opteed
69 MAP_OPTEE_PAGEABLE,
70 #endif
71 {0}
72 };
73 #endif
74
75 #ifdef IMAGE_BL2
76 static const mmap_region_t plat_rpi3_mmap[] = {
77 #ifdef MAP_SHARED_RAM
78 MAP_SHARED_RAM,
79 #endif
80 MAP_DEVICE0,
81 MAP_FIP,
82 #if MEASURED_BOOT && !TRANSFER_LIST
83 /* Legacy measured boot path: need BL1 RW mapping to access event log */
84 RPI3_MAP_BL1_RW,
85 #endif
86 MAP_NS_DRAM0,
87 #ifdef BL32_BASE
88 MAP_BL32_MEM,
89 #endif
90 #ifdef MAP_FW_HANDOFF
91 MAP_FW_HANDOFF,
92 #endif
93 {0}
94 };
95 #endif
96
97 #ifdef IMAGE_BL31
98 static const mmap_region_t plat_rpi3_mmap[] = {
99 #ifdef MAP_SHARED_RAM
100 MAP_SHARED_RAM,
101 #endif
102 MAP_DEVICE0,
103 #ifdef RPI3_PRELOADED_DTB_BASE
104 MAP_NS_DTB,
105 #endif
106 #ifdef BL32_BASE
107 MAP_BL32_MEM,
108 #endif
109 #ifdef MAP_FW_HANDOFF
110 MAP_FW_HANDOFF,
111 #endif
112 {0}
113 };
114 #endif
115
116 /*******************************************************************************
117 * Function that sets up the console
118 ******************************************************************************/
119 static console_t rpi3_console;
120
rpi3_console_init(void)121 void rpi3_console_init(void)
122 {
123 int console_scope = CONSOLE_FLAG_BOOT;
124 int rc;
125
126 if (RPI3_RUNTIME_UART != -1)
127 console_scope |= CONSOLE_FLAG_RUNTIME;
128
129 rc = rpi3_register_used_uart(&rpi3_console);
130
131 if (rc == 0) {
132 /*
133 * The crash console doesn't use the multi console API, it uses
134 * the core console functions directly. It is safe to call panic
135 * and let it print debug information.
136 */
137 panic();
138 }
139
140 console_set_scope(&rpi3_console, console_scope);
141 }
142
143 /*******************************************************************************
144 * Function that sets up the translation tables.
145 ******************************************************************************/
rpi3_setup_page_tables(uintptr_t total_base,size_t total_size,uintptr_t code_start,uintptr_t code_limit,uintptr_t rodata_start,uintptr_t rodata_limit,uintptr_t coh_start,uintptr_t coh_limit)146 void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size,
147 uintptr_t code_start, uintptr_t code_limit,
148 uintptr_t rodata_start, uintptr_t rodata_limit
149 #if USE_COHERENT_MEM
150 , uintptr_t coh_start, uintptr_t coh_limit
151 #endif
152 )
153 {
154 /*
155 * Map the Trusted SRAM with appropriate memory attributes.
156 * Subsequent mappings will adjust the attributes for specific regions.
157 */
158 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
159 (void *) total_base, (void *) (total_base + total_size));
160 mmap_add_region(total_base, total_base,
161 total_size,
162 MT_MEMORY | MT_RW | MT_SECURE);
163
164 /* Re-map the code section */
165 VERBOSE("Code region: %p - %p\n",
166 (void *) code_start, (void *) code_limit);
167 mmap_add_region(code_start, code_start,
168 code_limit - code_start,
169 MT_CODE | MT_SECURE);
170
171 /* Re-map the read-only data section */
172 VERBOSE("Read-only data region: %p - %p\n",
173 (void *) rodata_start, (void *) rodata_limit);
174 mmap_add_region(rodata_start, rodata_start,
175 rodata_limit - rodata_start,
176 MT_RO_DATA | MT_SECURE);
177
178 #if USE_COHERENT_MEM
179 /* Re-map the coherent memory region */
180 VERBOSE("Coherent region: %p - %p\n",
181 (void *) coh_start, (void *) coh_limit);
182 mmap_add_region(coh_start, coh_start,
183 coh_limit - coh_start,
184 MT_DEVICE | MT_RW | MT_SECURE);
185 #endif
186
187 mmap_add(plat_rpi3_mmap);
188
189 init_xlat_tables();
190 }
191
192 /*******************************************************************************
193 * Gets SPSR for BL32 entry
194 ******************************************************************************/
rpi3_get_spsr_for_bl32_entry(void)195 uint32_t rpi3_get_spsr_for_bl32_entry(void)
196 {
197 /*
198 * The Secure Payload Dispatcher service is responsible for
199 * setting the SPSR prior to entry into the BL32 image.
200 */
201 return 0;
202 }
203
204 /*******************************************************************************
205 * Gets SPSR for BL33 entry
206 ******************************************************************************/
rpi3_get_spsr_for_bl33_entry(void)207 uint32_t rpi3_get_spsr_for_bl33_entry(void)
208 {
209 #if RPI3_BL33_IN_AARCH32
210 INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n");
211 return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE,
212 DISABLE_ALL_EXCEPTIONS);
213 #else
214 return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
215 #endif
216 }
217
plat_get_syscnt_freq2(void)218 unsigned int plat_get_syscnt_freq2(void)
219 {
220 return SYS_COUNTER_FREQ_IN_TICKS;
221 }
222
plat_ic_get_pending_interrupt_type(void)223 uint32_t plat_ic_get_pending_interrupt_type(void)
224 {
225 ERROR("rpi3: Interrupt routed to EL3.\n");
226 return INTR_TYPE_INVAL;
227 }
228
plat_interrupt_type_to_line(uint32_t type,uint32_t security_state)229 uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
230 {
231 assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) ||
232 (type == INTR_TYPE_NS));
233
234 assert(sec_state_is_valid(security_state));
235
236 /* Non-secure interrupts are signalled on the IRQ line always. */
237 if (type == INTR_TYPE_NS)
238 return __builtin_ctz(SCR_IRQ_BIT);
239
240 /* Secure interrupts are signalled on the FIQ line always. */
241 return __builtin_ctz(SCR_FIQ_BIT);
242 }
243
244 #if MEASURED_BOOT || TRUSTED_BOARD_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)245 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
246 {
247 return get_mbedtls_heap_helper(heap_addr, heap_size);
248 }
249 #endif
250